# Conference Sessions

# Papers

Special: Nonlinear Dynamics in Cellular Wave Computing

Miklos Koller, András Horváth and Tamas Roska

Frameless computing for spatial-temporal events

The detection of spatial-temporal event detection is a difficult task in machine vision and it is usually difficult to be handled efficiently with current algorithms and devices. There are many examples in nature, like looming detection or detection of moving objects with given speed and trajectory, which shows that the human vision system can solve this extremely difficult task with simplicity and low power consumption. In this article we show examples how cellular neural networks can be used to detect spatial-temporal events. The detections are done by using continuous dynamics without cutting the input flow into frames. We can observe similar structures and functions -the detection of continuous input-flows with continuous dynamics- in the retina, which performs well and efficiently in image processing tasks.

Mauro Di Marco, Mauro Forti, Barnabas Garay, Miklos Koller and Luca Pancioni

Multiple Metastable Rotating Waves and Long Transients in Cooperative CNN Rings

This paper further investigates on the phenomena leading to the existence of long transient oscillations in a class of cooperative cellular neural network (CNN) rings. It is shown by means of analytic arguments, numerical simulations, and laboratory experiments, that the transients are due to the existence of several symmetric and nonsymmetric metastable rotating waves in the CNN ring which are strongly attracting along the stable manifold and weakly repelling along the unstable manifold.

Fernando Corinto, András Horváth and Tamas Roska

Architectures for Nanoscale Hybrid Computing Systems

Spin torque oscillator (STO) nanodevices have been brought into focus of engineering hoping they could provide for a platform of computation beyond Moore’s law. In this paper we propose hybrid-architectures (i.e. combining CMOS units and STO nanodevices) useful to realize Oscillatory Cellular Nonlinear Network (O-CNN) arrays that can be used for associative memory (AM) problem-solving. The fundamental components of the AM O-CNN are (1) a CMOS preprocessing unit generating input feature vectors from picture inputs, (2) an AM cluster generating signature outputs composed of spin torque oscillator (STO) cells and local spin-wave interactions, as an oscillatory CNN (O-CNN) array unit, applied several times arranged in space, and (3) a classification unit (CMOS). In this manuscript we focus on the AM cluster composed of several STO and we aim at showing how local spin-wave interactions lead to global indirect interactions. In addition, a mathematical methodology is proposed in order to design the fully-connected AM cluster of STO exploiting the local spin-wave interactions due to physical limits of the implementation.

Ramazan Yeniceri and Mustak Erhan Yalcin

The Doppler Effect with Input Driven Autowaves

The autowave, which is a kind of nonlinear wave, is easy to generate but difficult to control its source on networks. This paper proposes a new configuration of a Cellular Nonlinear Network and special constant valued input patterns in order to generate autowaves and control its source. It is also shown in this paper that the Doppler Effect is still observed on autowaves with moving source. In this paper, the input pattern is moved continuously to keep the continuity of the autowave evolution. Autowaves can solve the path planning problem with known techniques. Furthermore, the Doppler Effect provides a feature about source’s motion. Controlling the autowave source using only the inputs of the network is the novelty of this paper which increases the precision of tracking the source motion in CNN based path planning algorithms.

Special: Configurable Neuromorphic Systems

Stephen Nease, Stephen Brink and Jennifer Hasler

STDP-Enabled Learning on a Reconfigurable Neuromorphic Platform

Spike-Timing Dependent Plasticity (STDP) is a well-known mechanism that implements learning in biological neural networks. We have developed a neuromorphic integrated circuit which contains 100 neurons and 30,000 synapses, 20,000 of which can follow an STDP learning rule. This work presents the initial results for circuits utilizing STDP on this chip.

Saber Moradi, Nabil Imam, Rajit Manohar and Giacomo Indiveri

A Memory-Efficient Routing Method for Large-Scale Spiking Neural Networks

Progress in VLSI technologies is enabling the integration of large numbers of spiking neural network processing modules into compact systems. Asynchronous routing circuits are typically employed to efficiently interface these modules, and configurable memory is usually used to implement synaptic connectivity among them. However, supporting arbitrary network connectivity with conventional routing methods would require prohibitively large memory resources. We propose a two stage routing scheme which minimizes the memory requirements needed to implement scalable and reconfigurable spiking neural networks with bounded connectivity. Our routing methodology trades off network configuration flexibility for routing memory demands and is optimized for the most common and anatomically realistic neural network topologies. We describe and analyze our routing method and present a case study with a large neural network.

Hesham Mostafa, Federico Corradi, Marc Osswald and Giacomo Indiveri

Automated synthesis of asynchronous event-based interfaces for neuromorphic systems

We present an automated design approach that leverages the commonly available digital design tools in order to rapidly synthesize asynchronous event-based interface circuits from behavioral VHDL code. As part of the proposed design approach, we describe a verification methodology that is able to reveal early in the design process potential timing failures in the generated circuits. Due to the fast design cycle, the approach presented allows designers to quickly explore different architectures for asynchronous circuits and compare them using quantitative metrics based for example on power consumption or silicon area. We validated the proposed design method by synthesizing asynchronous interface circuits for a neuromorphic multi-neuron architecture, and fabricating the VLSI device. We present data from silicon that demonstrates the correct operation of the automatically generated circuits.

Matthias Hock, Andreas Hartel, Johannes Schemmel and Karlheinz Meier

An Analog Dynamic Memory Array for Neuromorphic Hardware

We describe an array of capacitor based cells capable of storing analog voltages and currents for highly configurable large-scale neuromorphic hardware. A novel refresh scheme based on content-addressable memory as well as a slow and simple voltage ramp generator is presented. The circuits have been simulated in a 65nm mixed-signal low power process. Key characteristics are an area consumption of 175 µm² and a power consumption of less than 125 nW per stored value. A prototype chip has been designed and submitted for fabrication.

Thomas Rost, Harshawardhan Ramachandran, Martin Paul Nawrot and Elisabetta Chicca

A neuromorphic approach to auditory pattern recognition in cricket phonotaxis

Developing neuromorphic computing paradigmsthat mimic nervous system function is an emerging field ofresearch with high potential for technical applications. In the present study we take inspiration from the cricket auditory system and propose a biologically plausible neural network architecture that can explain how acoustic pattern recognition is achieved in the cricket central brain. Our circuit model combines two key features of neural processing dynamics: Spike Frequency Adaptation (SFA) and synaptic short term plasticity. We developed and extensively tested the model function in software simulations. Furthermore, the feasibility of an analogue VLSI implementation is demonstrated using a multi-neuronchip comprising Integrate-and-Fire (IF) neurons and adaptive synapses.

Special: Memristor Technology in Nonlinear Dynamical Circuits

Fernando Corinto, Marco Gilli, Alon Ascoli and Ronald Tetzlaff

Complex dynamics in neuromorphic memristor circuits

A deep study of the nonlinear dynamics of nonlinear circuits with memristors represents a fundamental step towards the development of memristor-based systems for bio-inspired applications and dense nonvolatile memories. A rich variety of complex dynamic behaviors, including chaos, may be observed even in a simple memristor oscillator. This article is organized according to the regulations of the ECCTD 2013 Special Sessions. We present a short summary of the state-of-the-art of memristor theory, model and applications. In addition, we briefly introduce a comprehensive Nonlinear Circuit Theory-based foundation for circuit implementation of the Hodgkin-Huxley neural model with memristors.

Ádám Rák and György Cserey

Emulation of analog memristors using low yield digital switching memristors

In this paper, we propose circuits for emulating analog purpose memristors (APM) purely composed from digital switching memristors or digital purpose memristors (DPM). Our design is also robust against memristor defects therefore this can be applied even in low yield technology where defects occur at high probability. Our simulations show that the switching noise of the circuits decreases with the number of memristors and the production yield of the circuit is no lower than the production yield of the digital switching memristors.

Ella Gale, Ben Costello and Andy Adamatzky

Observation of Spontaneous Bursting Spike Patterns in Simple Three Memristor Circuits

The distinctive switching spikes seen in single memristor circuits can be suppressed in networks of memristors. Instead oscillatory behaviour interrupted by spontaneous irregular bursting spike patterns are observed. An investigation of two and three memistor circuits was undertaken to elucidate the origin and nature of these rich dynamics. No spiking or oscillations are seen in circuits where all the memristors are arranged with matching polarity. Spiking is seen in circuits where memristors are arranged anti-parallel. These dynamics may be due to increased sensitivity to initial conditions or deterministic chaos and are potentially useful for neuromorphic computing.

Arturo Buscarino, Luigi Fortuna, Mattia Frasca and Lucia Valentina Gambuzza

A new driven memristive chaotic circuit

The adoption of memristors in the design of chaotic circuits combines their intrinsic properties of being nonlinear and memory devices. Many different chaotic circuits have been, in fact, designed considering different types of nonlinearities modeling the memristor characteristic. In this work the model of a new non-autonomous circuit, designed starting from the topology proposed by Murali, Lakshmanan and Chua and replacing the Chua’s diode with two HP memristors in antiparallel is introduced.The memristor model adopted has been described by Strukov et al. and it is able to reproduce the behavior observed in the actual $TiO_2$ based memristor.The configuration considered in this work is based on two memristors in antiparallel which have been already proposed to build autonomouschaotic circuits.The numerical characterization obtained varying the parameters of the sinusoidal driving signal unveils a rich variety of dynamical behaviors, ranging from limit cycles to different regions of chaotic oscillations. The introduced model goes in the direction of designing non-autonomous chaotic circuits with a small number of components.

Sangho Shin, Kyungmin Kim and Sung-Mo Kang

Memristor Macromodel and Its Application to Neuronal Spike Generation

This paper introduces a memristor-based neuronal spike event generator, in which the memristor models the nonlinear behavior of opening and closing of sodium and potassium ion channels. The neuronal action potential describing both the integrate-and-fire spiking events and the refractory period of nerve membrane cells is enabled by utilizing dual time-constants offered by the bistable resistance state of practical memristive devices. A memristor macromodel which is capable of representing both the threshold effects and boundary assurance is also presented.

Analog Circuit Design 1

María De Rodanas Valero, Santiago Celma, Nicolas Medrano and Belen Calvo

OpAmp Design for Lock-in Amplifiers in Portable Sensing Systems

This paper presents a 1.2 V low-power rail-to-rail class AB operational amplifier (OpAmp) suitable for integrated lock-in amplifiers. The proposed OpAmp has been designed in a standard 0.18 μm CMOS technology. For a 1.2 V single supply and 81 μW power consumption, simulations shows a 86 dB open loop gain, 56º phase margin, 17 MHz unity gain frequency with 1 pF load and 97 dB CMRR. Adaptive biasing provides 33 V/μs slew-rate for a 1 pF capacitive load. A compact and reliable lock-in amplifier (LIA) has been designed using the proposed circuit. Post-layout results for noisy signals confirm the capability of the LIA to effectively recover information from signal-to-noise ratios down to -26 dB with errors below 4.2% up to 50 kHz and a power consumption of only 675 µW.

Fábio Passos, Helena Fino and Elisenda Roca

A Wideband Lumped-Element Model for Arbitrarily Shaped Integrated Inductors

In this paper a model based on lumped elements is used to characterize integrated inductors. The method proposed allows the modelling of integrated inductors for a wide range of frequencies, thus granting the overall characterization of the device and the evaluation of important design parameters such as inductance, quality factor and resonance frequency. The model can easily be applied to any polygonal shape inductor due to its inductance calculation through self and mutual inductances. Electromagnetic simulations results are presented to demonstrate the validation of the model.

Belen Calvo, Cristina Azcona, Nicolas Medrano, Santiago Celma and Maria De Rodanas Valero

A Compact Low-voltage First-order Temperature-compensated CMOS Current Reference

This paper presents the design of two new low-voltage first-order temperature compensated CMOS current references. To achieve compact topologies able to operate under low voltage with low power consumption, they are based on the simplest approach of cross-coupled current mirrors, and compensation is obtained by introducing a temperature dependent current mirror ratio. Results for 0.18 µm CMOS implementations show that the proposed 1 µA references operate with supplies down to 1 V showing temperature drifts below 238 ppm/ºC over the (–40 to 120 ºC) range, which makes them suitable for low-cost portable applications

Alfio Dario Grasso, Salvatore Pennisi and Gaetano Palumbo

Optimized Frequency Compensation Topology for Low-Power Three-Stage OTAs

A power-efficient frequency compensation topology for three-stage transconductance amplifiers is presented in this paper. Stability analysis and design equations are carried out based on the small-signal model. Unlike many recently reported solutions, the proposed architecture do not rely upon parasitic and/or pole-zero cancellation, thus providing a more robust design. As an example, the proposed technique was used to design a three-stage amplifier in a standard CMOS 65-nm technology. The amplifier achieves a 2-MHz gain-bandwidth product when driving a 1-nF capacitance by consuming only 82 uW from a 2.5-V supply. Simulation results are found in good agreement with theoretical analysis and show an improvement in both small-signal and large-signal amplifier performance over previously reported solutions.

Elton N. Lima, José Luis Cura and Luis Nero Alves

Folded-Cascode Transimpedance Amplifiers Employing a CMOS Inverter as Input Stage

This paper presents the design and comparison of two shunt feedback transimpedance amplifiers (TIAs)implemented in standard 350nm CMOS technology from Austria Microsystems. These transimpedance amplifiers are based on a folded cascode topology. The first one is a conventional folded-cascode (CFC-TIA) and the second is a modified version folded-cascod (MFC-TIA) employing a CMOS inverter at the input stage. The proposed MFC-TIA achieves a gain of 80dBΩ, 370MHz bandwidth and minimum input current noise of 1,6pA√Hz with 0.5pF total input capacitance. The achieved results show that MFC-TIAs can match the performance of CFC-TIAs with reduced implementation area, thus being a suitable solution for high density circuits.

Analog Circuit Design 2

Benedikt Schlecker, Georg Fantner, Maurits Ortmanns and Jens Anders

Novel Electronics for High-speed FM AFM in Life Science Applications

In this paper we present a novel system architecture for high-speed FM-AFM electronics. The proposed system consists of a PLL-based FM-demodulator preceded by a SSB modulator and driving electronics ensuring a stable self-oscillation of the cantilever. Thanks to the SSB upconverion preceding the FM-demodulator, the system allows for demodulation bandwidths as large as the cantilever resonance frequency, opening up the way to real-time FM-AFM of biological processes. Electrical measurements of a PCB-based prototype verify the proposed architecture.

Khaled Aggour and Renato Negra

Study of peak and backoff efficiency of different power amplifier classes in outphasing systems

In this paper, we present an outphasing power amplifiersystem. The system performance is studied and analysed.The peak power efficiency and backoff power efficiency arecompared for three classes of operation, class-D, class-E andclass-F. Class-D power amplifier shows superior efficiency at bothmaximum power (95 %) and at backoff power. At 10 dB backoffpower from peak power, efficiency is simulated to be 60 % . Aproposed phase modulation improves the efficiency at backoffpower by 7-8 % . A CMOS class-D version is proposed to testthe system implementation feasibility in CMOS technology andits performance is reported. The maximum efficiency is found tobe around 70 % and the 5 dB backoff power efficiency is about 35 %.

Jon Håvard Eriksrød and Trond Ytterdal

A 65nm CMOS Front-end LNA for Medical Ultrasound Imaging with Feedback Employing Noise and Distortion Cancellation

A 70uW low power front-end Low Noise Amplifier (LNA) for ultrasound applications is proposed. The amplifier utilizes a balun based on a common-gate (CG) and a common-source (CS) combination. The CS-amplifier performs error correction, and thus cancels distortion and noise from the CG-amplifier. The amplifier is optimized towards low noise and low power consumption, and is a capacitive micro machined ultrasonic transducer (CMUT) tailored LNA. The LNA is design and simulated under 65nm CMOS technology, achieving a noise figure (NF) of only 2.87dB with a total power consumption of only 70uW . The amplifier is tuned towards an CMUT impedance of 10k<-60deg at a center of frequency 5MHz, with a input impedance of 3.2k. Moreover, sporting a dynamic range (DR) of 40.57dB.

Sara Pashmineh, Stefan Bramburger, Hongcheng Xu, Maurits Ortmanns and Dirk Killat

An LDO using stacked transistors on 65 nm CMOS

This paper presents a low drop-out voltage regulator (LDO) suitable for input voltages twice the nominal operating voltage of the CMOS technology. High GBW and good DC accuracy in line and load regulation is achieved by using 3-stage error amplifiers. Two feedback loops are used to improve stability. High voltage compatibility is established by stacking two pass transistors. The first pass transistor is controlled by the main error amplifier; the 2nd pass transistor is controlled by 2nd amplifier adjusting the division of the voltages between the two pass transistors. The paper presents circuit design and simulations results of a LDO with 500 mA output current using the 2.5 V transistors of the TSMC 65 nm CMOS low-power process technology.

Yan Huang and Dirk Killat

Design and analysis of novel dynamic latched comparator with reduced kickback noise for high-speed ADCs

A novel dynamic latched comparator with reduced kickback noise for high-speed ADCs is presented. Dynamic latched comparators suffer from kickback noise. Especially the common-mode kickback noise becomes even more critical in the application. By using input common source transistors and the self-isolated mechanism the novel dynamic latched comparator produces much lower common-mode kickback noise, while the differential kickback noise is also reduced. The simulated results show that the proposed comparator not only produces the common-mode kickback noise less than one third of other typical dynamic latched comparators, but also performs faster.

Biomedical Circuits

Ralph L. Stoop, Florian Gomez, Rolf Schönenberger, Claude Baumann and Ruedi Stoop

Parameter properties of electronic and biological circuits and systems

The question what behaviors can be exhibited by a given electronic circuit upon variation of the parameters, is fundamental to electrical engineering. To efficiently adapt behavior according to need, say from stability to instability, or among stable or unstable periodicities, it is crucial to know how systems (generically and specifically) depend on parameters. Shrimps or swallow-tails are generic, characteristic parameter space regions that yield fixed stable periodic behavior. By dividing the parameter space into stable and unstable dynamical behavior, they provide such guidelines. In applications, shrimps have first been described at great details in the context of laser systems and electronic circuits, but it is still unknown whether they could also be found in realistic models of biophysics (and if so, whether biology exploits this as an alternative computing paradigm). Here, we provide first explicit examples of their existence.

Sara Ghoreishizadeh, Sandro Carrara and Giovanni De Micheli

A Configurable IC to Contol, Readout, and Calibrate an Array of Biosensors

We present a novel integrated circuit for a biosensing data acquisition chain. The circuit controls and reads out five bimolecular sensors as well as pH and temperature sensors for biosensor calibration. The IC supports both chronoamperometry (CA) and cyclic voltammetry (CV) measurements, which are commonly used in biosensing. Different voltage waveforms are generated to control CV by using a single configurable waveform generator and programmable constant voltage levels are producedto enable CA. To reduce the area and power consumption of the interface electronics, a unified circuit is designed for CV, CA and pH readout. The biosensors produce currents that are converted by a 13.5-bit sigma delta analog to digital converter.The circuit has been designed and realized in 0.18 μm technology. It consumes 711 μW from a 1.8 V supply voltage, making it suitable for remotely powered and implantable applications.

Surya Sharma and Trond Ytterdal

A Low Power Analog RAM Implementation for In-Probe Beamforming in Ultrasound Imaging

An Analog RAM architecture for beamforming based on switched current circuits is presented. The proposed architecture allows the sharing of the same bias current for different memory cells, hence results in a large amount of power saving. The beamformer consists of total 16 channels and in each channel a delay line with depth of 16 has been implemented. The input frequency is 10MHz and a sampling frequency of 25MHz is used. The proposed architecture achieves 50dB of dynamic range and 49dB of SNDR with power dissipation of 760µW for one channel. The ARAM is implemented in 180nm CMOS technology and occupies 250×150µm2 per channel

Pawel Turcza

Low Power 2 Mbps Radio Telemetry System for Biomedical Applications

The paper presents a low power telemetry system for neural recording applications. The presented system operates in the 433 MHz ISM band. It offers a 2 Mbits/s throughput using a continuous phase frequency-shift keying (CPFSK) modulation. The presented transmitter is based on a free running, modified complementary Colpitts oscillator. Instead of using a separate power amplifier to drive the antenna, the VCO incorporates a loop antenna as its inductive element. To compensate for the oscillator frequency pulling due to changes in the antenna’s environment, supply voltage or temperature, a wide band high performance digital receiver was developed. The presented transmitter was implemented using a 180 nm CMOS process, and consumes just 450 uW.

Sensors & Actuators 1

Daehyuk Kim, Inkyung Hwang, Jaeyoung Bae and Minkyu Song

A High Dynamic Range CMOS Image Sensor with a Digital Configurable Logarithmic Counter

Many kinds of high dynamic range (HDR) CMOS Image Sensors (CIS) have been reported, such as a multiple sampling, a multiple exposure technique, and so on. However, those techniques have some drawbacks of noise increasing, large power consumption, and huge chip area. In this paper, a new digital configurable logarithmic counter is described. Since the proposed scheme is easily implemented with a simple algorithm, we can reduce power consumption and chip area drastically. Further, the logarithmic counter enhances the dynamic range (DR) by 24dB. The chip which has been fabricated using a 0.13um CIS process achieves a 57.6dB SNDR at 50kS/s.

Alfio Dario Grasso, Salvatore Pennisi, Mario Paparo and Davide Patti

Estimation of In-Cylinder Pressure Using Spark Plug Discharge Current Measurements

In-cylinder pressure of spark ignition engines is correlated with several variables of the compression, injection, and ignition processes. Therefore, by monitoring the pressure of each cylinder we can improve the electronic engine supervision and control in terms of fast response and accuracy, thus enabling online diagnosis and overall efficiency improvement. However, the pressure measurement methods proposed until now have not been generally accepted at the production level due to their cost and/or complexity. In this paper we describe a novel approach that derives the pressure information from the measurement of the ordinary spark plug discharge current. In this manner, the mechanical part of the engine does not require substantial modification. To demonstrate the viability of the proposed technique, a prototype measurement system was set up and tested. Preliminary experimental data show that pressure in stationary conditions can be estimated with an error lower than 5% for pressure above 3 atmospheres.

Manuel Suárez, Víctor Manuel Brea, Diego Cabello, Jorge Fernández, Ricardo Carmona and Ángel Rodríguez

A 176×120 Pixel CMOS Vision Chip for Gaussian Filtering with Massivelly Parallel CDS and A/D-Conversion

This paper conveys a proof-of-concept chip for Gaussian pyramid generation for image feature detectors. Gaussian filtering and image resizing are performed with a switched-capacitor (SC) network. The chip is conceived as the mapping of a CMOS-3D architecture for feature detectors onto a conventional technology, with some functionality removed, and the corresponding area overhead with respect to a CMOS-3D architecture, but preserving masivelly parallel Correlated Double Sampling (CDS) and A/D conversion. The chip has been fabricated on a die of 5×5 mm² with 0.18 μm CMOS technology, achieving an array of 176×120 sensing elements (pixels). The pixels are arranged in Processing Elements (PEs). Every PE comprises four photodiodes, four SC nodes, one CDS circuit, and local circuitry for one ADC. Every PE occupies an area of 44×44 μm². The chip senses an image and computes the Gaussian pyramid with an average power consumption lower than 75 nW/pixel at 30 frames/s.

Panagiotis Giounanlis, Elena Blokhina, Orla Feely, Manuel Dominguez, Joan Pons-Nin and Sergi Gorreta

Modelling of a Charge Control Method for Capacitive MEMS

Charging of dielectric materials in microelectromechanical systems (MEMS) actuated electrostatically is a major reliability issue. In our previous work we proposed a feedback loop control method that is implemented as a circuit and that allows smart actuation for switches and varactors. In this paper we discuss system-level modeling of MEMS devices including all aspects of the system: proposed control method, charging dynamics and realistic models of the mechanical components of MEMS.

Gianluca Giustolisi, Gaetano Palumbo, Paolo Finocchiaro and Alfio Pappalardo

A simple extraction procedure for determining the electrical parameters in Silicon Photomultipliers

The Silicon Photomultiplier (SiPM) is a promising kind of device able to handle single photons thus permitting the measurement of weak optical signals. The design of a high-performance front-end electronics for the read-out, requires an accurate electrical model of the SiPM. A reliable model was developed in the past but the parameter extraction procedure is rather cumbersome and requires several measurement steps. In this communication we present a simple extraction procedure that can be performed with two simple measurement steps. The extraction procedure is applied to a 10×10 SiPM and is validated by comparing the equivalent spice model to measurement results.

Memristive Circuits

Weiran Cai, Ronald Tetzlaff and Frank Ellinger

Critical Role of Initial Condition in the Dynamics of Memristive Systems: Orbital Narrowing Revisited

This paper explores the characterization of memristive systems utilizing the characteristive curve of state and analyze the special role of initial condition in such history-dependent systems. The specifically studied system focuses on the titanium dioxide memristor based on the nonlinear ionic drift model of Joglekar. We derive first the characteristic curve of state (CCOS) as the analytical solution of the model to any integer index in the Gaussian hypergeometric form, based on which a characterization approach is then developed. The approach simply converts the complicated history-dependent dynamics into a mapping on the state-flux phase plane, expressing the initial condition as a pure translation along the flux axis, which is analogous to the characterization method for transistors. With this geometric view, we observe that the initial condition operates as an operation point for a memristive system and can effectively influence the orbital shape: the same input signal can produce two distinct orbital shapes when the initial conditions differ. From another point, there ought to be two factors giving rise to the orbital narrowing phenomenon: the frequency and the initial condition. It is pointed out that this is purely caused by the nonlinearity in the model.

Alon Ascoli, Fernando Corinto, Vanessa Senger and Ronald Tetzlaff

Insights on memristor modeling

This work sheds some light into the crucial discussion over which memristor model should be adopted in the design of memristor-based electronic circuits. In a first study, taking the Pickett’s model as reference, for a documented circuit and input setting some of the most acknowledged memristor models are fitted to it by means of an optimization procedure. The second study shows how the dynamics of basic memristor circuits may strongly depend on the memristor model under use. The development of a more universal memristor model is thus necessary for the progress of memristor-based IC design. Here we present some preliminary result on a new modeling approach based on polynomial series expansion.

Kristin Majetta, Christoph Clauß, Torsten Schmidt and Ronald Tetzlaff

Application of Tool-Specific Simulation Algorithms to Memristor Models Written in Modelica

In 2008 a physical device that contained a layer of titanium dioxide located between platinum electrodes became known as the HP-Memristor. Many models of this device, in different degrees of abstraction, were presented in the literature. This paper describes the simulation of some of these models, written in the object oriented language Modelica, with different numerical algorithms and gives an overview of their efficiency and stability.

Adrian Walsh, Raymond Carley, Orla Feely and Alon Ascoli

Memristor Circuit Investigation through a new Tutorial Toolbox

This paper presents a new tutorial toolbox for exploration of memristor circuits, developed in the MATLAB and Simulink environments. It is aimed at students, researchers, designers and anybody interested in memristors and their applications. The toolbox allows users to build and simulate memristor circuits, and some novel results obtained through use of the toolbox are presented.

Valeri Mladenov and Stoyan Kirilov

Analysis of the mutual inductive and capacitive connections and tolerances of memristor’s parameter’s of a memristor memory matrix

In this paper the mutual inductive and capacitive connections and tolerances of memristor’s parameter’s of a memristor memory matrix is investigated. An equivalent circuit of three neighboring memristors of a memory matrix with complicated mutual capacitive and inductive connection is presented. Then the memristor’s own parasitic capacitance and inductance are described. The mutual capacitances between the rims of the memory matrix are calculated. Two possible values of the coefficient of magnetic coupling between the memristors are used. A SIMULINK model of the circuit of three neighboring memristors is developed. The simulation is made at pulse mode with 3 GHz actuating voltages. The main result is that the parasitic parameters do not strongly affect the memristor voltage drops at frequencies up to 3 GHz. However the tolerances of the memristor parameters have stronger effect on the circuit characteristics. Finally, some concluding remarks associated with the magnetic and capacitive influence between the memristors of a memristor memory matrix are given.

Sensors & Actuators 2

Pramath Keny, Arya Menon, Madhura Rao, Urvang Gaitonde, Animesh Gupta and Sriharsha Annamaneni

Development of Antenna Deployment Circuit for Nano-Satellites

Nano Satellites generally weighing between 1 and 15 kg, serving the purpose of space research are popularly standardized as CubeSats. The CubeSat standard has made it really feasible and easy for students from various universities to develop their own Nano-satellites with their very own payloads. Antennas are critical components in the onboard communication system of satellites, the Nano Satellites usually communicate in the Amateur Frequency Bands; these bands exist from 144 MHz to 146 MHz in VHF and from 434 MHz to 438 MHz in the UHF range. Designing antennas at these frequencies typically ends up being larger in size than the actual CubeSat itself. Thus generally the antennas for a Nano Satellite are made flexible enough to be folded in order to comply with the CubeSat size standards. Once the satellite is ejected into the orbit from the deployer module, an automated signal is used to trigger a circuit that initiates a series of processes to deploy the folded antennas back into their original shape. This paper deals about the design and development of a highly efficient, smart and reliable control circuit prototype called the Antenna Deployment Circuit. This developed prototype is tested and the results are summarized in the paper.

Yusuke Yamamoto, Keiji Kato, Lei Lin and Masahiro Fukui

A Thermal Management System for Lithium-ion Battery in Mobile Systems

Mobile systems with lithium-ion batteries have become very popular. Higher performance, longer battery life, and safer operation are required for those systems. We have developed a method of the thermal management system for lithium-ion batteries for mobile systems. An evaluation system has been built with micro-processor with analog interface, and FPGA. It provides a charge and discharge speed control to manage the temperature condition. An application to variable speed charger shows that battery can be charged in short time with less temperature rise.

Beatriz Blanco-Filgueira, Paula López, Manuel Suárez and Juan B. Roldán

CMOS photodiode model and HDL implementation

With CMOS image sensors scaling down due to the resolution and miniaturization demands, compact models for these devices become essential. A physically based model can be used to optimize the device performance and allow circuit designers to use these sensors in integrated circuits. Among other capacities, this analytical model can be used to predict with high accuracy the best photodiode geometry to achieve the maximum photoresponse while optimizing the total layout area cost.

Cristina Azcona, Belen Calvo, Nicolas Medrano, Santiago Celma and Carlos Sánchez-Azqueta

A CMOS Quasi-digital Temperature Sensor for Battery Operated Systems

This paper presents a high performance 1.2 V – 0.18 µm CMOS quasi-digital temperature sensor with frequency output suitable to be used in battery operated systems. The proposed sensor is based on a multivibrator current-to-frequency converter and works properly over a temperature range of –40 to +120 ºC, with a minimum power consumption of 1.8 µW. It presents a linear response, with a sensitivity of 442 Hz/ºC. Recovered temperature values show accuracy better than 1.7 ºC.

Peng Wang, Thomas Halvorsrød and Trond Ytterdal

A Low Noise Single-Ended to Differential Linear Charge Sampling SC-VGA for Second Harmonic Cardiac Ultrasound Imaging

A low noise single-ended to differential linear switched capacitor variable gain amplifier (SC-VGA) is designed in a 0.18μm CMOS technology for 4MHz center frequency (f_c) ultrasound imaging. To fit the higher source impedance from gradually scaled piezo-electric transducers (PZT) in ultrasound imaging systems, a charge sampling amplifier with a fixed integration time as the first stage exhibits lower noise, and higher sensitivity comparing to conventional voltage sampling amplifiers. The second voltage sampling stage converts the single-ended input to differential outputs with an exponential gain control which exploits an 8b binary capacitor DAC array, and the gain varies dB-in-linear from -14dB to 14dB. For reducing the capacitance spread for a binary-weighted 8b (1:256) DAC array, the array is segmented between the upper 4b and lower 4b by a divider capacitor. Simulation results show the analog part of proposed amplifier consumes 1.25mA at 1.8V, has HD2 -68dB, HD3 -89dB at 150mV output Vpp, and the input referred noise (IRN) is 6.56pA/√Hz at 4MHz and 25.3nArms at a sampling frequency (f_s) of 30MHz. The active layout size is 310μm×370μm.

Special: Applications of Mathematical Methods in Circuits and Systems Design

Angela Slavova

Stabilization of coupled reaction-diffusion CNN

In this paper we first present brief overview of the state of the art in mathematical modeling concepts and methodologies for circuits and systems design. Coupled FitzHugh-Nagumo neural system is studied. First we construct Cellular Nonlinear Network (CNN) discretized model of the system under consideration. For this model the edge of chaos domain of the parameter set is obtained. Stabilization of the discretized model is proposed by feedback control which is simple for implementations.

Xavier Vilasis-Cardona and Mireia Vinyoles-Serra

More on the Generalized Fisher Discriminant Based in 2 Neuron Cellular Neural Networks

We discuss on the possibilities of a statistic to be used in hypothesis testing which uses the convergence map of a two-neuron cellular neural network with piece-wise linear activation function, presented in reference [1]. We present a deeper discussion on the variations of the method, its use in pattern recognition, and particularly, the extension of the problem to higher dimensions.

Tang Tang and Ronald Tetzlaff

Applying Cellular Neural Networks Dynamics for Image Representation

In this paper we discuss in detail the feasibility of implementation and realization of uncoupled Cellular Neural Networks (CNN) systems for image representation. Applying CNN systems for representation of binary image patterns with sparse distribution of points as an example for a possible application example is studied here. The test results show a high quality of representation with this method and proved it to be a possible way to implement the proposed CNN structures in practical application.

Kiyotaka Yamamura and Hideki Tanaka

Finding All Solutions of Piecewise-Linear Resistive Circuits Using Separable Programming

A new algorithm is proposed for finding all solutions of piecewise-linear resistive circuits using separable programming. In this algorithm, the problem of finding all solutions is formulated by a separable programming problem, and it is solved by the modified simplex method using the restricted-basis entry rule. Since the modified simplex method finds one solution per application, the proposed algorithm can find all solutions efficiently. Numerical examples are given to confirm the effectiveness of the proposed algorithm.

Luigi Fortuna, Mattia Frasca and Maria Gabriella Xibilia

A class of generalized orthonormal functions

In this paper a new class of orthonormal functions which includes as particular case the Laguerre filters are introduced. These functions are defined as the product of a fixed transfer function of order n and of an all-pass filter of order n x h for any n and h. The orthogonality of these functions is proven in the general case. Moreover, the singular values of the sum of the first Nh members of this class are shown to be all equal to the orthonormalization constant.

Special: Problems and Solutions on Mega Core Array Architectures

Csaba Nemes, Gergely Barcza, Zoltán Nagy, Örs Legeza and Péter Szolgay

Implementation trade-offs of the density matrix renormalization group algorithm on kilo-processor architectures

Numerical analysis of strongly correlated quantum lattice models has a great importance in quantum physics. The exponentially growing size of the Hilbert space makes these computations difficult, however sophisticated algorithms have been developed to balance the size of the effective Hilbert space and the accuracy of the simulation. One of these methods is the density matrix renormalization group (DMRG) algorithm which has become the leading numerical tool in the study of low dimensional lattice problems of current interest. In the algorithm a high computational problem can be translated to a list of dense matrix operations, which makes it an ideal application to fully utilize the computing power residing in both current multi-core processors and novel kilo-processor architectures.

Bence J. Borbely, Zoltán Kincses, Zsolt Vörösházi and Péter Szolgay

Analysis of myoelectric signals using a Field Programmable SoC

A platform design for the analysis of human myoelectric signals (MES) is presented. Offline recorded multi- channel signals of forearm muscles are processed with a Field Programmable SoC in order to classify different movement pat- terns to control human-assisting electromechanical systems with multiple degrees of freedom (e.g. a prosthetic hand). Benchmark results of an ANSI C implementation are shown to assess the raw performance of the built-in ARM cores of the SoC. Possible computational bottlenecks are located based on the results and custom hardware implementations are shown to fully utilize the flexibility and performance of the used hardware platform.

Andras Kiss, Zoltan Nagy and Gyorgy Csaba

FPGA-implementation of a Holographic Pattern-matching Algorithm

In this paper, we demonstrate the FPGA implementation of a massively parallel, non-Boolean pattern-matching algorithm. The algorithm is based on the concepts of optical computing: quasi-optical wave equations are solved numerically, using FPGA-accelerated hardware. The FPGA-based wave-equation solver is very well parallelizable, so the resulting pattern-matching algorithm will also be amenable to mega-core architectures.

Osman Levent Savkay, Nerhun Yildiz, Evren Cesur, Mustak Erhan Yalcin and Vedat Tavsanoglu

Realization of Preprocessing Blocks of CNN Based CASA System on FPGA

In this paper, hardware optimization of the preprocessing part of a computer aided semen analysis (CASA) system is proposed, which is also implemented on an FPGA device as a working prototype. A real–time cellular neural network (CNN) emulator (RTCNNP–v2) is used for the realization of the image processing algorithms, whose regular, flexible and reconfigurable infrastructure simplifies the prototyping process. For future work, the post–processing part of the CASA system is proposed to be implemented on the same FPGA device as software, using either a soft or hard processor core. By the integration of the pre– and post–processing parts, the designed CASA system will be capable of processing full–HD 1080p@60 (1080×1920) video images in real–time.

Andreas Krinke, Maximilian Mittag, Göran Jerke and Jens Lienig

Extended Constraint Management for Analog and Mixed-Signal IC Design

The consideration of a growing number of design constraints is becoming a bottleneck in the design of analog and mixed-signal integrated circuits and is blocking more, much-needed automation in this area. In this paper, we propose a solution to these issues with a new methodology for constraint propagation and transformation. This technique allows designers and software tools to consider all relevant constraints when modifying a design, regardless of where these constraints were originally created. We integrated our ideas in an industrial design flow. The implementation of an electrical constraint type demonstrates the practical relevance. With constraints of this type the ON resistance of power stages in smart power ICs can be limited for the first time.

Circuit Analysis 1

Zbigniew Galias and Xinghuo Yu

Discretization effects in single input delayed sliding mode control systems

Discretization effects of sliding mode control systems with a delay are studied. We investigate the existence of periodic solutions, the influence of the delay on the period and amplitude of steady state oscillations, and the structure of basins of attraction of different periodic orbits. Theoretical results are illustrated with simulation examples.

Pekka Miettinen, Mikko Honkala, Janne Roos and Martti Valtonen

Realizable Reduction of Interconnect Models

with Dense Coupling

This paper describes a model-order reduction (MOR) method to reduce an interconnect circuit with possibly dense inductive and capacitive coupling. The method uses partitioning to divide the original circuit into small parts that can be then approximated accurately with low-order reduced-order models (ROMs). The use of low-order ROMs enables the use of positive-valued macromodels with standard RLCK realization. The coupling is reduced with a two-stage reduction separately for the inductive and capacitive coupling. This allows for efficient sparsification of the coupling effect. The method is verified with test simulations of the 65-nm technology node and is shown to produce good reduction results in terms of CPU speedup and generated error.

Lubomir Brancik

Simulation of Hybrid MTL Systems with Random Parameters based on Stochastic DAEs

The paper deals with a method for the simulation of hybrid systems containing multiconductor transmission lines (MTL) with randomly varying primary parameters. A core of the method lies on a theory of stochastic differential equations (SDE) considering the system responses as stochastic processes. In fact, due to a hybrid nature of the system containing also parts with lumped parameters, a system of stochastic differential-algebraic equations (SDAE) is obtained. The responses are formed by the sets of stochastic trajectories completed by corresponding sample means and confidence intervals. The MTL model is based on a cascade connection of generalized RLCG T-networks and a state-variable method is used to formulate its equations. The boundary conditions are folded in by a modified nodal analysis (MNA) enabling to include the MTLs as parts of arbitrary lumped-parameter circuits. Finally, a backward differentiation formula consistent with the Itô stochastic calculus is used for numerical solutions. All the computer simulations were performed using the Matlab language.

Carsten Wegener

Method of Modeling Analog Circuits in Verilog for Mixed-signal Design Simulations

Simulating mixed-signal circuit designs needs to bridge between the analog and digital circuit domains. Preserving the behavior and structure of the analog and digital parts of the circuit is possible with Hardware Description Languages (HDLs), such as Verilog-AMS. However, the analog and digital parts of the design are typically developed in simulation environments tailored to either the analog or digital design flow requirements. For digital circuit development, Verilog is a popular choice of HDL. Including the analog part of the mixed-signal circuit in the Verilog description without the AMS extension requires a modeling strategy that can preserve fundamental analog behavior. In this contribution we describe a method of modeling analog sub-circuits in Verilog. The higher-level analog circuit is modeled by netlisting the connectivity of sub-circuits based on a schematic. This method of modeling and hierarchical netlisting is scalable and demonstrated for the example of an Analog-to-Digital Converter (ADC). We can simulate the digital design interacting with the analog circuit on any standard Verilog simulator, thus, (proprietary) language extensions are not required.

Tetsuo Nishi, Siegfried Rump and Shin’Ichi Oishi

A consideration on the condition number of extremely ill-conditioned matrices

As for a matrix $A$ we examine two problems: (a) To find the upper and the lower bound of $mbox{Cond}_{2}(A)$ in terms of two coefficients $p_1$ and $p_{n-1}$ of the characteristic polynomial of $AA^T$, and (b) proof of existence of a matrix $A$ having considerably larger condition number than that obtained in the previous papers. The connection between (a) and (b) is illustrated.

Circuit Analysis 2

Mikko Honkala, Pekka Miettinen, Janne Roos and Martti Valtonen

Admittance parameter formulation for realizable model-order reduction

This paper proposes an admittance formulation for improving the stability of the structure-preserving reduced order interconnect macromodeling algorithm SPRIM and the RLC equivalent circuit synthesis method RLCSYN. A simulation example is presented to show the benefits of admittance formulation.

Carlos Formigli, Riccardo Rovatti and Gianluca Setti

Power Grid Dispatch Policies and Robustness to Chain Failures

We explore how blackout sizes change when power dispatching of is done using some uneconomical policies that seek to reduce loading of transmission lines. The uncoupled DC models of IEEE power grids test cases 30, 57 and 118 are used to show the effect of the studied policies.

Mark Gourary, Sergey Ulyanov and Michael Zharov

Model Order Reduction by State Vector Selection (SVS) Approach

A new approach to construct multipoint projection-based model order reduction algorithms is proposed. The approach is aimed to decrease the redundancy of the reduced model and to provide an effective error control. The generation of the projective matrix is performed using worst-case analysis to determine frequency point, input excitation and internal state vector corresponding to the maximal value of the user-defined error norm. The value of the norm also provides the error control and stopping criterion. Numerical results of the comparison of the proposed approach with known methods PRIMA and PMTBR are presented.

Pier Paolo Civalleri, Marco Gilli and Michele Bonnin

The Spatial CAUCHY Problem for a Dissipative Infinite Quantum Waveguide Supporting a Single Propagating Mode

We consider an infinite waveguide supporting a single propagating mode for which the excitation (say the electric or the magnetic field) is assigned in a given section assumed as the origin of the coordinate z along its axis. In steady state the state evolution along z is the solution of the spatial CAUCHY problem along such coordinate. As soon as the radiation involves a low number of photons, or even reduces to a single one, the classical treatment must be replaced by a quantum one. Moreover the effect of dissipation must be taken into account by either a microscopic treatment of the properties of the dielectric material and of the metallic boundaries, or, as long as only the mathematical form of the equations be of interest, by using a spatial version of LINDBLAD equations. We choose here the second alternative. From the obtained equations it is possible to extend the treatment to multimode finite terminated waveguides.

Martin Wolkerstorfer and Steffen Trautmann

Sequential multiobjective optimization for large-scale passive filter synthesis

We propose a generic method for handling coupling among subsystems in large-scale multiobjective analog circuit synthesis. It is based on sequentially solving multiobjective optimization problems for each subsystem. The approach is exemplified on a pure feasibility problem of black-box passive filter design for a communications application. A proof-of-concept for the proposed method is provided through simulation. The practical outcome is a well-selected set of alternative design choices that all fulfill the pre-specified filter design constraints.

Analog RF Circuits & Design

Anu Lehtovuori and Risto Valkonen

Strategies for Finding a Bandwidth-Optimal Topology for Impedance Matching

When searching for an impedance matching circuit yielding the maximum bandwidth with certain number of matching elements, the choice of the correct topology is crucial. Compared to optimal two-element (L-section) matching, the improvement of bandwidth provided by a third element can be anything from negligible to significant. In this paper, two approaches for finding an optimal three-element matching circuit are proposed. The first method is a simple optimization based search for promising matching topologies. The second method systematically searches the optimal matching topology and analyzes the bandwidth provided by the alternatives. Numerical results with example real-life loads are presented to demonstrate the importance of the topology choice in impedance matching.

Noboru Maeda, Shinji Fukui, Toshikazu Sekine and Yasuhiro Takahashi

An Estimation Method for the 3 Port S-parameters with 1 Port Measurements

An estimation method of the three-port S- parameters for reciprocal circuits is presented. In this method, several known loads are connected to two of the ports and reflection characteristic of the remaining port is measured. Therefore, there is no need to connect network analyzer to the ports which are connected to the known loads. S-parameters are obtained by solving a linear system equations and quadratic equations only. In addition, applying this method to estimate the S-parameters of an immunity test system, validness of this method has been confirmed.

Kim Östman, Mikko Englund, Olli Viitala, Kari Stadius, Jussi Ryynänen and Kimmo Koli

Design Tradeoffs in N-path GmC Integrators for Direct Delta-Sigma Receivers

This paper analyzes a tradeoff between noise figure, blocker filtering, and noise shaping that is inherent in the recently introduced direct delta-sigma receiver approach. It originates in the competing requirements imposed by the front-end low noise amplifier operating as a transconductor in an N-path GmC integrator and as a voltage pre-amplifier in a closed-loop radio-frequency front-end. A generic receiver model for evaluating the tradeoff is presented and verified through simulation. We then propose a design method for managing the tradeoff in light of receiver target specifications.

Quoc-Tai Duong and Jerzy Dabrowski

Focused Calibration for Advanced RF Test with Embedded RF Detectors

In this paper a technique suitable for on-chip IP3/IP2 RF test by embedded RF detectors is presented. A lack of spectral selectivity of the detectors and diverse nonlinearity of the circuit under test (CUT) impose stiff constraints on the respective test measurements for which focused calibration approach and a support by customized models of CUT is necessary. Also cancellation of second-order intermodulation effects produced by the detectors under the two-tone test is required. The test technique is introduced using a polynomial model of the CUT. Simulation example of a practical CMOS LNA under IP3/IP2 RF test with embedded RF detectors is presented showing a good measurement accuracy.

Fahad Qazi Qazi, Duong Quoc Tai and Jerzy Dabrowski

Blocker and Image Reject Low-IF Frontend

Abstract—In this paper we present a design of a low-IF receiver frontend using a selective N-path filter which serves blocker rejection, image rejection, and downconversion. The filter makes use of quadrature impedance upconversion technique using multiphase clocking and can be programmed by baseband capacitance- and gm-cell transconductance values to meet the low-IF criterion in various cases. Presented is both a mathematical model of the filter and circuit simulation results including parasitic effects. Image rejection of 14 dB at IF that is provided by the filter mitigates the demands for the ultimate image rejection by the IQ mode. The blocker rejection at IF is larger than 50 dB. Designed in in 65 nm CMOS the low-IF receiver frontend with a modified N-path filter in simulations achieves NF < 6 dB and OOB IIP3 > +8 dBm in 0.5-1 GHz band.

Digital RF Circuits & Design

Geza Kolumban, Tamas Krebesz, Francis C. M. Lau and Chi K. Tse

Turn your baseband Matlab simulator into a fully functional, 2.4-GHz, operating FM-DCSK transceiver using SDE platform

In Software Defined Electronics (SDE), the software and hardware components are completely separated. Every information processing system from communications to measurement engineering is implemented in BaseBand (BB) on a SW platform and the interface between the baseband and RF/microwave domains is assured by a universal HW device. Due to the universality of HW device, the implementation of different RF/microwave equipment requires only the change of SW in the application layer.

Matlab simulators are used to evaluate the feasibility and performance of new signal processing algorithms and equipment everywhere from the academia to industry. This contribution shows how a Matlab BB simulator developed to determine the system performance of an FMDCSK transceiver can be integrated directly into the SDE platform. The usability and the effectiveness of SDE approach is verified by comparing the simulated BB and measured 2.4-GHz microwave signals.

Enrico Roverato, Marko Kosunen, Jerry Lemberg, Tero Nieminen, Kari Stadius, Jussi Ryynänen, Petri Eloranta, Risto Kaunisto and Aarno Pärssinen

A Configurable Sampling Rate Converter for All-Digital 4G Transmitters

This paper presents a digital interpolation chain for non-integer variable-ratio sampling rate conversion, targeted to 4G mobile applications. Such a system is needed in all-digital transmitters, where the sampling rate of the digital input to the RF front-end must be an integer fraction of the carrier frequency. A highly configurable architecture is proposed to cope with the flexibility needed in 4G applications. The system achieves excellent ACLR of 75 dB, EVM degradation of 0.05%, and RX-band noise below -160 dBc/Hz. Digital synthesis of the circuit in a 40nm low-power CMOS process results in a core area of only 0.073 mm2. The estimated power consumption is between 6 and 29 mW, depending on channel bandwidth and transmission band.

Hongjia Mo and Michael Peter Kennedy

A High-Throughput Spur-Free Hybrid Nested Bus-Splitting/HK-MASH Digital Delta-Sigma Modulator

By virtue of its smaller bus, a nested bus-splitting DDSM has a potential speed advantage over its conventional counterpart. However, it can also suffer from poorer spur performance, especially in the case of constant and/or periodic inputs. By combining the features of nested bus-splitting and HK-MASH, a hybrid structure can retain the speed advantage while being simultaneously spur-free. This paper introduces the hybrid DDSM architecture and discusses its performance.

Rakesh Gangarajaiah, Liang Liu, Michal Stala, Peter Nilsson and Ove Edfors

A High-Speed QR Decomposition Processor for Carrier-Aggregated LTE-A Downlink Systems

This paper presents a high-speed QR decomposition(QRD) processor targeting the carrier-aggregated 4 × 4 Long Term Evolution-Advanced(LTE-A) receiver. The processor provides robustness in spatially correlated channels with reduced complexity by using modifications to the Householder transform, such as decomposing-target redefinition and matrix real-valued decomposition. In terms of hardware design, we extensively explore flexibilities in systolic architectures using a high-level synthesis tool to achieve area-power efficiency. In a 65 nm CMOS technology, the processor occupies a core area of 0.77 mm2 and produces 72 MQRD per second, the highest reported throughput. The power consumed in the proposed processor is 127 mW.

Tamas Krebesz, Geza Kolumban, Francis C. M. Lau and Chi K. Tse

Application of universal software defined PXI platform for the performance evaluation of FM-DCSK communications system

A specific method for the application of a universal software defined wireless platform is presented to determine system performance of communications system based on real field tests. On the platform every application can be implemented: the transmitter and the receiver establishing a wireless link, the communications channel and the algorithm to determine system performance. Implementation is done in software that offers flexible, efficient and cheap solution for performance testing. Every physical RF analog signals generated or processed in software can be recovered on the PXI hardware platform used in our tests. Since the analog RF output and input of the transceiver are available, real field tests can be performed or even the system performance can be evaluated in a real operating network. Using the PXI platform, based on real field tests the evaluation of system performance of a 2.4-GHz ISM band wireless communication system with FM-DCSK modulation is presented here. A systematic method for the validation of system implemented on the PXI HW is provided.

Mixed-signal Circuit Design and Converters 1

Christoph Zorn, Tina Thiessen, Timon Brückner, Maurits Ortmanns and Wolfgang Mathis

State Space Analysis of Mixed Signal Systems with Switched Feedback and Delay

This paper discusses how switching delay or respectively excess loop delay affects the dynamics of sampled systems with discrete control. It is presented how a switched system model enables an analytical description ofthe maximum states in dependency of the input amplitude, the system coefficients and delay. Furthermore, this paper provides an analytical method to scale the maximum states to a specific value in order to reduce the increased dynamics caused by the delay.

Izzet Cem Göknar, Shahram Minaei, Merih Yildiz and Ergul Akcakaya

Pulse Width Modulation Using a Recently Developed CMOS Core Circuit

In this paper a new approach for a Pulse Width Modulation (PWM) circuit operating in current-mode using a CMOS classifier core circuit, and its application to level crossing are presented. The proposed architecture is much simpler than existing PWM methods and the generated PWM signal can be controlled electronically through the control currents of a core circuit. Measurements performed with DU-TCC 1209*, an IC designed and manufactured using 0.35 µm AMS technology parameters, show a perfect match.with theoretical results.

Ryo Matsushiba, Hiroaki Kotani and Takao Waho

An Energy-Efficient ΔΣ Modulator Using Dynamic-Common-Source Integrators

An energy-efficient ΔΣ modulator has been investigated by using dynamic common-source integrators. Instead of the virtual short commonly used in conventional opampbased integrators, the novel integrator used the fact that when a MOSFET turns off from its on-state, the voltage difference between two terminals connected to the gate and source approaches to its threshold voltage, which is virtually constant after the charge redistribution. No static currents flow in the present integrator, resulting in high energy efficiency. An FOM of 29 fJ/comv-step was estimated by our transistor-level circuit simulation assuming 0.18-μm standard CMOS technology with an SNDR, a bandwidth and a sampling frequency of 82.6dB, 20 kHz and 5 MHz, respectively.

Shaileshsingh Chouhan and Kari Halonen

A Modified Cross Coupled Rectifier based Charge Pump for Energy Harvesting using RF to DC conversion

This paper presents with a CMOS based RF-to-DC converter using a proposed cross-coupled charge pump for energy harvesting. Extraction of high DC voltages from rectifier block in the charge pumps is always a serious bottleneck for RF energy scavenging. One of the dominant obstacle is the threshold voltage (Vth) of the MOS transistor. In this work we are proposing a simple mechanism to eliminate the Vth dependence in MOS transistor, which inherently improves the DC extraction ability of charge pump. The proposed system is implemented in 180nm CMOS technology and simulated using Cadence Spectre. The extracted DC voltage from RF energy is selected as Figure of Merit. It is found using simulation that the modified charge pump shows a high efficiency in DC extraction from RF signal than the conventional cross coupled rectifier based charge pump

Chenzi Huang, Frank Woittennek and Klaus Röbenack

Steady-State Analysis of a Distributed Model of the Buck Converter

For the well-known buck converter, we replace the inductor and capacitor by a transmission line. In other words, the lumped reactive elements are substituted by a distributed element. This results in a completely different type of the model. Instead of ordinary differential equations as for the classical buck converter, we obtain a set of partial differential equations with appropriate boundary conditions. The stationary regime of both models is compared in theoretical investigations and simulation studies.

Mixed-signal Circuit Design and Converters 2

Federico Bizzarri, Angelo Brambilla, Vincenza Ferrara, Giambattista Gruosso, Giancarlo Storti Gajani and Luca Viganò

Efficiency Improvement of Partially Shaded Photovoltaic Panels

Layouts of domestic photovoltaic solar plants can be problematic due to obstacles that shade panels. This limits the total available area and, if not adequately considered, can deeply affect the efficiency of the plant. In this paper, a circuit that recovers generated power efficiency when a small number of cells of a panel are partially or totally shaded is proposed. This circuit is constituted by DC/DC converters that are connected in parallel to cells and that balance power generation. Simulation results and experimental measurements performed on a prototype version of the circuit are reported and described together with its advantages and drawbacks.

Peng Wang, Thomas Halvorsrød and Trond Ytterdal

A Low Noise Single-End to Differential Switched-Capacitor VGA for PZT Xducer Ultrasound Imaging

A low noise single-ended to differential linear two-stage switched capacitor variable gain amplifier (SC-VGA) is designed in a 0.18μm CMOS technology for 4MHz center frequency (f_c) ultrasound imaging. To simplify the clock generator and improve linearity, voltage sampling technique is adopted to replace charge sampling for sake of the source impedance of piezo-electric transducers (PZT) not being as high as capacitive micro-machined ultrasonic transducers (CMUT) in ultrasound imaging systems. The two-stage VGA based on a single stage OTA to save the power, and controlled by the 10-bit digital signals, has the maximum dB-in-linear gain varied from -14dB to 32dB. The first stage converts the single-ended input to differential outputs with a 2-bit 6dB/step coarse gain control varying from 0dB to 18dB, and the second stage has a fine gain control which exploits an 8b binary capacitor DAC array varying from -14dB to 14dB. For reducing the capacitance spread for a binary-weighted 8b (1:256) DAC array, the array is segmented between the upper 4b and lower 4b by a divider capacitor. Simulation results show the core analog part of two-stage VGA consumes 900μA at 1.8V, has HD2 -80.94dB, HD3 -70.06dB at 200mV output Vpp, and the input referred noise (IRN) is 10.25nV/√Hz at 4MHz at a sampling frequency (f_s) of 30MHz. The active layout size is 387μm×502μm.

Matteo Biggio, Federico Bizzarri, Angelo Brambilla, Giorgio Carlini and Marco Storace

Reliable and Efficient Phase Noise Simulation of Mixed-Mode Integer-N Phase-Locked Loops

In this paper the results obtained by performing the Periodic Noise (PNoise) analysis of a Phase-Locked Loop (PLL) modeled as a mixed analog/digital circuit are compared with those from experimental measurements. The PNoise analysis of this class of circuits is done by considering them as hybrid dynamical systems. Since the circuit simulators available on the academic and industrial shelves are not able to carry out this kind of simulation, experimental validation is mandatory to support numerical results and enforce the reliability of the proposed approach. A significant improvement of the PNoise analysis efficiency, in terms of reducing its computational burden when it is used to simulated noise in PLLs with a large frequency ratio, is also presented, which allows to more easily manage the noise folding phenomenon.

Thi My Hanh Nguyen and Tadashi Tsubone

Stabilizing Control based on Stability Transformation Method for Switching Power Converter

A dynamic controller based on Stability Transformation Method (STM) has been used to stabilize unknown unstable periodic orbits (UPOs) in dynamical systems. The advantage of the control method is that it can stabilize the UPOs without information of location about the target orbit. In this study, we introduce a novel control method based on STM to stabilize UPOs in DC-DC switching power converter. The idea of the proposed method is to apply temporal perturbations to switching time, where the perturbation can be calculated exactly by using a dynamic controller based on STM. Therefore, our control method can stabilize unknown UPOs. The effectiveness of proposed method is verified by theoretical analysis and circuit simulator.

Johannes Görner, Johannes Uhlig, Stefan Haenzsche and René Schüffny

Behavioral Model of a Continuous Current Integrator with Time Discrete Feedback and Sampling

This paper proposes an analytical model for current integrator with a continuous current input signal, a continuous voltage output signal, with time discrete feedback and sampling. Such an integrator is suited as first integrator within a delta sigma modulator performing analog to digital conversion of a current input signal. Capacitive or current feedback can be used for keeping the integrator within the range of operation. The model considers slew-rate and bandwidth limited settling, parasitic capacitances, and non-linear effects. Simulink is used to explore the circuit design space for the first integrator of a 4th order hybrid incremental delta sigma modulator.

Semiconductor Devices and Technology

Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Tsung-Yi Ho and Yu-Chuan Chen

Lithography-Aware 1-Dimensional Cell Generation

As the process technology advances to the sub-wavelength era, the 1-dimensional (1-D) design style is regarded as one of the most effective ways to continue scaling down the minimum feature size. This paper presents the lithography-aware cell generation algorithms which simultaneously minimize 1-D cell area and enhance the printability. Experimental results show that the proposed algorithms can effectively and efficiently reduce the number of diffusion gaps, and minimize used routing tracks. Consequently, our approach results in smaller 1-D cell area and better printability.

Nandakishor Yadav, Sunil Dutt, Manisha Pattanaik and G. K. Sharma

Double-Gate FinFET Process Variation Aware 10T SRAM Cell Topology Design and Analysis

Static Random Access Memory (SRAM) has been under it’s rebuilding stage in nanoscale era, pioneer aiming to rebuff the increased process variation and Short Channel Effects (SCE). In this paper, FinFET 10T process tolerant differential access and ultra low voltage operation SRAM cell topology is proposed. Back-gate biasing is used to manipulate gate work-function to extract variation aware and low power design. Built-in feedback mechanism is employed to achieve variation tolerance design during read operation. Monte-Carlo simulations for 5000 points with 3-sigma equivalent to 10% deviation from mean value are executed to quantify the effectiveness of proposed cell. Compared to a standard 6T Cell, we obtain 4.7times and 1.9times improvement in RNM and SNM, respectively, with a 3.5% diminishment in WM. Moreover, RNM and WM are augmented by 6.5% and 3.6%, respectively, against PPN10T cell.

João Capela Duarte, Ernesto Ventura Martins and Luis Nero Alves

Frequency Characterization of Memristive Devices

This paper proposes a new methodology suitable for frequency characterization of memristive devices (MDs) and systems. MDs are usually described by their associated hysteresis loops. Their distinctive memory properties stem from this unusual characteristic. Understanding the frequency behavior of these devices is of paramount importance for a multitude of different applications. This paper presents a morphological method suitable for the analysis of the frequency dependency of hysteretic loops. The proposed approach considers the area and the length of the loop dependence on frequency. An application example, considering thin film TiO2 MDs is considered for illustration and discussion.

Valeri Mladenov and Stoyan Kirilov

Syntheses of a PSpice Model of a Titanium-dioxide Memristor and Wien Memristor generator

In this paper a PSpice model of the equivalent circuit of the titanium-dioxide memristor’s is presented based on the current-voltage relationship. By use of this model a Wien memristor generator is created. The oscillator circuit is analyzed and the basic time diagrams are given. The phase portrait of the system is also presented. The regulation of the output voltage magnitude and of the frequency is realized by changing the memristor states. In the end, some concluding remarks associated with the tolerances of possible changing of memristor parameters with respect to the operation of the Wien memristor are given.

ADC & DAC

Sarang Kazeminia, Obalit Shino, Ehsan Haghighi and Khayrollah Hadidi

~~Improved Single-Stage Kikback-Rejected Comparator for High Speed and Low Noise Flash ADCs~~

No presentation due to visa problems.

In this paper, the conventional single-stage latched comparator is improved for both high speed and low noise flash ADCs. In the proposed method for high-speed applications, the common mode level of output voltage is preserved unchanged during both amplification and latch operations, to speed up the comparison of small voltage differences. Also, the amplitude of digital control signals is reduced in the modified low-noise comparator by using a fully differential structure to remove the concern of digital noise coupling on analog section. Worst-Case simulation results for all corners, using the BSIM3 model of a 0.35µm CMOS process, confirm that a 5mv differential input can be simply detected and recovered to full range values, at 800MS/s and 500MS/s update rate, consuming around 780µW and 650mW in high speed and low noise comparators, respectively. This is equivalent to about 60% improvement in the speed of the conventional single-stage comparator. Also, the amplitude of the control signals is reduced to about 18% of full range values, from 3.3v to 0.6v, by using the proposed low noise structure. High speed and low noise comparators can be implemented in 288µm2 and 480µm2 active area, respectively.

Elbert Bechthum, Georgi Radulov, J. Briaire, Govert Geelen and Arthur van Roermund

A novel output transformer based highly linear RF-DAC architecture

A major limitation of the linearity of Current Steering (CS) RF-DACs is the large output voltage swing (typically 1Vpp), which couples to sensitive internal nodes and thereby causes non-linear distortion. This paper proposes a novel approach for the linearization of the CS RF-DAC. An output transformer decouples the output from the circuit core and attenuates the voltage swing seen by the RF-DAC current cells. A lumped element model of a transformer is used in calculations and simulations to analyze the performance of the transformer in the Mixing-DAC application, and to select optimal design parameters for high linearity. Verification with a simulation model of an RF-DAC shows that the output related non-linearity (IMD3) of the CS RF-DAC improves with about 14dB when the proposed transformer parameters are used.

Samuel Sordo-Ibáñez, Blanca Piñero-García, Servando Espejo-Meana, Antonio Ragel-Morales, Joaquín Ceballos-Cáceres, Manuel Muñoz-Díaz, Luis Carranza-González, Alberto Arias-Drake, José Miguel Mora-Gutiérrez and Miguel Ángel Lagos-Florido

An Adaptive Approach to On-Chip CMOS Ramp Generation for High Resolution Single-Slope ADCs

Many image sensors employ column-parallel ADCs in their readout structures. Single-slope ADCs are ideally suited for these multi-channel applications due to their simplicity, low power and small overall area. The ramp generator, shared by all the converters in the readout architecture, is a key element that has a direct effect in the transfer characteristic of single-slope ADCs. Because a digital counter is inherently present in this conversion scheme, one common practice is to use a digital-to-analog converter driven by the counter to generate the ramp. Given the direct relationship between the DAC and the ADC transfer characteristics, one of the main issues is to ensure a sufficient linearity of the DAC, with special emphasis on its monotonicity. Very often, in particular when medium to high resolutions are aimed, this requires calibration of the DAC, which must be repeated every once in a while to account for temperature, process, power supply, and aging variations. This paper presents an inherently monotonic ramp generator with high levels of linearity and stability against any expected source of variations, combined with a very efficient realization and an inherent automatic adaptability to different resolutions. The ramp generator has been designed using radiation hardening by design (RHBD) techniques, allowing its use in space applications.

Inkyung Hwang, Daehyuk Kim, Ju Hyun Roh, Mun Kyo Lee, Sun Phil Nah and Minkyu Song

An 8-b Cascaded Folding A/D Converter with a New Fully Differential Source Follower

Conventionally, source followers have been used at the block of track-and-hold amplifiers (THA) for high-speed medium-bit analog-to-digital converters (ADCs). Even though the input signals of an ADC are fully differential, two single-ended source followers should be normally used. This is because differential source followers have some drawbacks. In this study, a wideband fully differential source follower is presented to obtain maximum efficiency of a fully differential THA. Because a cross coupling technique at the differential nodes is adopted, the performance of the proposed source follower is superior to the performance of conventional followers. The result of Spurious Free Dynamic Range(SFDR) is -66.92dBc for Fin=Fs/2 at FS=500MHz. The SFDR of the proposed source follower is better by about 8.6dB than the SFDR of a conventional source follower under the same experimental conditions. To verify them, an 8-b cascaded folding ADC which includes the proposed source follower is fabricated with a 0.13um CMOS technology.

Rengarajan Ragavan, Anand Narayanan, Mikael Bengtsson and Quoc Tai Duong

A 0.35μm CMOS 6-bit Current Steering DAC

This paper presents the design and experimental results of a high speed, low-power, thermometer coded and current steered 6-bit digital-to-analog converter. It is based on hybrid architecture with a switched current matrix controlled by the four most significant digital bits, and a conventional 2-bit current source controlled by the two least significant bits. The DAC occupies 0.15 mm2 chip area in standard 0.35 μm CMOS technology. A spurious-free dynamic range (SFDR) of 25 dB has been measured over the complete Nyquist interval at sampling frequencies up to 800 MS/s with a power consumption of 165 mW at 3.3 V power supply.

Oscillators 1

Jens Anders and Maurits Ortmanns

Frequency noise of CMOS LC tank oscillators operating in weak inversion

In this paper, we present an analytical model for a CMOS LC tank oscillator with its active devices operating in weak inversion. Our model combines nonlinear, stochastic circuit analysis in the form of the so-called stochastic averaging method proposed by Stratonovich with advanced MOS device modeling in the form of the EKV-model. The presented approach not only provides — for the first time — simple, yet accurate closed-form expressions for the oscillation frequency and amplitude of a CMOS LC tank oscillator operating in weak inversion but also allows us to derive closed-form expressions for the phase and frequency noise of the oscillator originating from both the parasitic resistance of the tank coil and the white noise generated in the cross-coupled MOS transistor pair. Thanks to their relatively compact and closed form, the presented results can not only be used for circuit optimization during the initial design phase but also convey important insights into the dependency of phase noise on design parameters such as the transconductance of the active devices.

Erik Lindberg

Oscillators – a simple introduction

Oscillators are kernel components of electrical and electronic circuits. Discussion of history, mechanisms and design based on Barkhausens observation. Discussion of a Wien Bridge oscillator based on the question: Why does this circuit oscillate ?

Muhammad Asfandyar Awan, Malik Summair Asghar, Zhen Huang, Wenyuan Li, Michael Peter Kennedy, Prof. Antonio Buonomo and Alessandro Lo Schiavo

An LC CMOS Injection-Locked Frequency Divider for Divide-by-Two and Divide-by-Three Operation

Numerous circuit topologies have been proposed for divide-by-m injection-locked frequency dividers (ILFDs), most of which have been optimized for division by even numbers, especially divide-by-2. It has been more difficult to realize division by odd numbers, such as divide-by-3. This paper describes a CMOS injection locked frequency divider (ILFD) that can operate equally well in both divide-by-two and divide-by-three modes. The ILFD is based on a cross-coupled CMOS LC-tank oscillator having capacitive and direct injection via both NMOS and PMOS transistors connected across the LC tank. The circuit is similar to a conventional CMOS ILFD for divide-by-two operation with direct injection, but it combines the effects of two independent injection techniques to maximize the width of its divide-by-three locking range. The paper presents the circuit architecture, SPICE simulations, and experimental measurements.

Wolfgang Mathis, Daniel Stahl and Richard Mathis

Oscillator Synthesis based on Nambu Mechanics with Canonical Dissipative Damping

Although circuit synthesis is one of the main subjects of circuit theory only a few systematic synthesis procedures are known for nonlinear circuits. Obviously, some of the difficulties for developing synthesis concepts for these circuits are related to theirs nonlinearities. In this paper we discuss a new mathematical concept for nonlinear differential equations that can be useful for the synthesis of a certain class of oscillator circuits. For this purpose we use Nambu mechanics where a system of differential equations can be constructed from a collection of invariants of movement (e.g. energy) and add a canonical dissipative damping term. It can be shown that the solution set of the system includes a stable limit cycle with prescribed properties. We illustrate our concept by means of an example.

Arturo Buscarino, Luigi Fortuna, Mattia Frasca and Marco Iachello

A new oscillator scheme for analog modeling

In this paper, a new nonlinear oscillator is analysed and the design of an analogue circuital implementation is discussed. The dynamical behaviour of the mathematical model is studied applying the harmonic balance principle and deriving the condition on system parameters necessary to observe stable nonlinear oscillations. The corresponding circuit has been designed taking into account and exploiting the non-ideal characteristics of both passive and active circuital components. The oscillations produced by the circuit have been characterized by varying a single parameter. Finally, the importance of the proposed system for in representing physical phenomena occurring in fusion plasmas is stressed, opening the way for the definition of a new strategy for improving plasma instabilities models.

Oscillators 2

Jakub Gronicz, Lasse Aaltonen, Nikolai Chekurov, Marko Kosunen and Kari Halonen

A 1.8 MHz MEMS-based oscillator with synchronous amplitude limiter.

This paper describes the design and simulation of a MEMS-based oscillator using a synchronous amplitude limiter. The proposed solution does not require external control signals to keep the resonator drive amplitude within the desired range. The interface electronics has been implemented and simulated in 0.35 μm HV CMOS process. The resonator was fabricated using a custom rapid-prototyping process involving Focused Ion Beam masking and Cryogenic Deep Reactive Ion Etching.

Michele Bonnin and Fernando Corinto

Evaluating the influence of noise on the spectrum of an oscillator

Phase models are practical tools to investigate the phase noise in stochastic oscillators. Traditional phase models describe the phase noise problem as a diffusion process, but experiments and simple solvable models reveal that white noise can also induce a frequency shift in the spectra of oscillators. In this paper we explain why traditional phase models fail to capture noise induced frequency shift and we present an improved phase model that explains this phenomenon. We develop a method for the direct calculation of the mean oscillation frequency and the power spectral density of stochastic oscillators. Our method can be applied to a wide class of stochastic oscillators. The validity of our theoretical predictions are confirmed by extensive numerical simulations.

Masoud Babaie and Robert Staszewski

A Study of RF Oscillator Reliability in Nanoscale CMOS

In this paper, we investigate the nature of oxide breakdown and stress-related degradation mechanisms in MOS transistors. The MOS breakdown time is quantified based on exponential-law and defect-generation models versus the oxide-thickness, gate area, temperature and voltage stress at a given cumulative failure. As a consequence, a design guide is presented to estimate the time dependent dielectric breakdown of any analog circuit. Based on reliability analysis, the lifetime of the recently-introduced class-F oscillator is evaluated for both thin and thick oxide options in 65-nm CMOS process.

Jingcheng Zhuang and Robert Bogdan Staszewski

Gain Estimation of a Digital-to-Time Converter for Phase-Prediction All-Digital PLL

We propose a gain estimation technique of a digital-to-time converter (DTC) and a time-to-digital converter (TDC) intended for an all-digital phase-locked loop (ADPLL) that is based on a recently introduced phase-prediction (PP) technique. Such a PP-ADPLL reduces the timing range and thus complexity of the fractional part of the phase detection mechanism. The conventional TDC gain estimation methods based on measuring the DCO clock period are not feasible for PP-ADPLLs due to the TDC timing range being much smaller than one DCO clock period. The proposed gain estimation method can run concurrently with the normal ADPLL phase locking process and its feasibility is confirmed through behavioral simulations. Although the estimation method is specifically proposed for the PP-ADPLL, its operating principle can also be applied to conventional ADPLL architectures that require an accurate TDC gain estimation.

Digital Circuit Design

Francesco Brandonisio, Alberto Prodomo, Michael Peter Kennedy and Ettore Napoli

Implementation of a Pulse-Holding Time-to-Digital Converter on an FPGA

In this work, we describe the implementation of a pulse-holding Time-to-Digital Converter (TDC) on a Xilinx Spartan 6 FPGA. We describe the operation of a pulse-holding TDC and we compare it with that of a pulse-shrinking TDC, which is the most similar TDC in the literature. We then illustrate a Simulink model of a pulse-holding TDC and the TDC that was implemented on a FPGA. The pulse-holding TDC uses a moving average filter to remove the quantization noise and improve the precision of the measurements. We show from simulations and experiments that the maximum modulus of the difference between the the input and output of the TDC can be reduced from 2 ns to less than 70 ps by means of a moving average filter.

Cancio Monteiro, Yasuhiro Takahashi and Toshikazu Sekine

Low Power Secure CSSAL Bit-Parallel Multiplier over GF(2^4) in 0.18um CMOS Technology

In this paper, we present the post layout simulation result of our previously proposed charge-sharing symmetric adiabatic logic (CSSAL) in comparison with the symmetric adiabatic logic, 2N-2N2P, and the TDPL in the bit-parallel cellular multiplier over GF(2^4). The transitional supply current and the power fluctuation of each logic style are compared in order to verify the logic ability for resistance against side-channel analysis attacks in cryptographic hardware implementation. The full custom layout is designed in cadence virtuoso IC6.1 with the chip size of 172×155 um^2, and the cyclical power consumption of 14 pJ at 12.5 MHz using 0.18 um CMOS technology for the CSSAL multiplier has achieved, while TDPL has 183×173 um^2 of the chip size, and the power consumption is 122.6 pJ which is about nine times higher than the one of the CSSAL. The low-power adiabatic logics are also thoroughly investigated, and the comparative data demonstrate that the proposed CSSAL multiplier has similar performance on power reduction and resistive to thwart side channel analysis at low frequency application.

Raul Jimenez, Manuel Sanchez, Trinidad Sanchez and Juan Antonio Gomez

FPGA-based implementation of a real-time timing measuring device

The design and implementation of a frequency meter that operates in real-time is presented. It has been implemented in a low cost FPGA device, concretely a SPARTAN-3AN700. The measuring device is configurable in resolution time and maximum measurable period. The main characteristics of the frequency meter are a minimum resolution time of 2.60 ns and a minimum measurable period of four times the resolution time.

Hongjia Mo, Michael Peter Kennedy, Vincent O’brien and Brendan Mullane

Experimental Validation of DAC with Nested Bus-Splitting EFM4 DDSM

This paper presents measured results for a fourth order nested bus-splitting Error Feedback Modulator (EFM4) with dynamic element matching and a four-bit DAC. The nested bus-splitting EFM4 can run approximately 38% faster than a conventional EFM4 on a Xilinx Virtex 5, with negligible degradation in spectral performance

Daisuke Takago, Ryo Sakai, Shuitsu Matsumura and Tsuyoshi Takebe

A Construction Method of Optimum Integer-to-integer Transform based on an Error Propagation Model

In lossless image compression, a ladder network is sometimes used for a integer to integer transform(integer transform). In such case, to reduce the difference between the real and the integer transform (transform error) caused by the influence of rounding operators and multipliers, the coefficients of multiplier should be small. We previously proposed a method of exchanging the rows of transformation matrix(row exchange method) to make the ladder network coefficients smaller. Although there are a lot of row exchange patterns, in this paper we propose a method that maximize the absolute value of trace of submatrix of the transformation matrix to find efficiently a better exchange pattern.

Signal Processing

Ilkka Nissinen, Jan Nissinen and Juha Kostamovaara

A time-gated 4×128 SPAD array with a 512 channel flash 80 ps-TDC for pulsed Raman spectroscopy

A time-gated 4×128 single photon avalanche diode (SPAD) array with a 512 channel flash time-to-digital converter (TDC) has been designed and realized for pulsed Raman spectroscopy in a high voltage 0.35 µm CMOS technology. The time-to-digital converter uses a coarse digital delay line with an interpolation structure to achieve a resolution better than the gate-delay of the technology. The delay lines are stabilized by using replica delay lines. The arrival of photons can be measured channel wise with a resolution and range of 80 ps and 3.5 ns, respectively. The maximum variation of the 80 ps resolution through the spectral rows was measured to be ± 33 ps. The main error source of Raman spectroscopy measurement, a high fluorescence can be rejected effectively with this resolution when a typical used pulse width of the laser is approximately 150 ps.

Akio Tsuneda and Kota Morikawa

A Study on Random Bit Sequences with Prescribed Auto-Correlations by Post-Processing Using Linear Feedback Shift Registers

There are several attempts to use chaotic nonlinear maps for random number generation. Theoretically, some chaotic maps can produce balanced and i.i.d.(independent and identically distributed) binary sequences. Also, chaotic binary sequences with prescribed auto-correlations can be generated. However, it is difficult to generate aperiodic sequences with prescribed auto-correlation properties by analog circuits or digital circuits only. In this paper, we propose a simple post-processing by linear feedback shift registers for generating random bit sequences with prescribed (positive/negative) auto-correlations. We perform some numerical experiments for investigating the effects of the proposed post-processing.

Pavel Máša, Pavel Sovka, Miroslav Vlček and Radim Špetík

Using ADZT for signal reconstruction

The Approximate Discrete Zolotarev Transform (ADZT) was described recently. The aim of this study is to describe possibilities and limitations of the ADZT for signal reconstruction in comparison with the DFT signal reconstruction. The signal reconstruction is shown for three types of signals using one signal segment with no need of overlap-add (or save) technique. Unlike the DFT synthesis vectors, the ADZT synthesis vectors are signal dependent. There is only one constraint that these vectors are given by the inversion of the linear combination of the DFT base vectors. This fact forms the main difference between the DFT and ADZT synthesis. The signal-dependent base of the ADZT brings some advantages but also some new problems with intepretation of results.

Mihály Radványi and Kristóf Karacs

Autonomous detection of information patterns through hierarchical peeling

Finding useful information in real world scenes is very important for many scene understanding tasks. Signs, scripts, information panels, and logos typically stand out from their environment for a human observer, but algorithmically locating them seems to depend on the actual context. We propose a hierarchical method that locates potentially interesting areas and examines whether their content is worth further examination. The algorithm digs into the containers by iteratively peeling down external shells and deciding what parts constitute the foreground. The proposed algorithm can be efficiently implemented on topographic processor arrays, since it mostly contains standard topographic instructions. The effectiveness of the approach is demonstrated through several examples.

Levent Aksoy, Eduardo Da Costa, Paulo Flores and Jose Monteiro

Exploration of Tradeoffs in the Design of Integer Cosine Transforms for Image Compression

In image data compression, integer cosine transforms (ICTs) have been preferred to discrete cosine transforms (DCTs) due to their similar transform efficiency and lower implementation cost. However, there exist many alternative ICTs with different performance measures and implementation costs. In this work, we explore all possible ICTs, compute their performance measures, and find their implementation costs in terms of the number of adders/subtractors, where a state-of-art technique is used to realize ICTs under a shift-adds architecture. We also investigate the tradeoff between performance and implementation cost, present the pareto-optimal points of this tradeoff, and introduce promising ICTs that were not considered before.

Cellular Neural Networks

Robert Braunschweig, Jens Müller, Jan Müller and Ronald Tetzlaff

NERO Mastering 300k CNN Cells

A novel massively-parallel fine-grain architecture featuring a digital emulation of Cellular Nonlinear Networks (CNN) is presented. A virtual cellular network is processed line-by-line by a locally connected linear array of processing elements. The resulting computing system is able to execute complex CNN program code consisting of consecutive operations. Furthermore we present a scalable FPGA implementation of this architecture for currently up to 480×640 cells with a precision up to 18 bit.

Chihiro Yoshimura, Masanao Yamaoka, Hidetaka Aoki and Hiroyuki Mizuno

Spatial Computing Architecture Using Randomness of Memory Cell Stability under Voltage Control

A new computing architecture based on a ground-state search of the Ising model and the probabilistic behavior of a memory cell is proposed. To improve computer performance, a spatial computing architecture that defines an Ising model as the interface between software and hardware is proposed. Various problems can be represented as a spatial parameter in the Ising model. A memory-cell-array-based hardware is utilized to search for the ground state of the Ising model. The interaction between memory cells produces a state transition to lower energy, and the randomness of memory-cell stability at lower voltage helps escape from a local minimum. It was verified by simulation that the proposed architecture can solve practical problems such as factorization and the traveling-salesman problem.

Przemyslaw Mroszczyk and Piotr Dudek

Trigger-Wave Propagation in Arbitrary Metrics in Asynchronous Cellular Logic Arrays

This paper presents the idea of an asynchronous cellular pixel-parallel logic array for global image processing tasks using trigger-wave propagation in medium with the hardware-controlled metric. The principles of wave propagation in the cellular four-connected logic arrays emulating different distance measure norms are explained and verified using a simplified switched RC circuit model. The proposed gate array consists of only 13 transistors per pixel and was implemented in a standard 90 nm CMOS technology. It provides the propagation medium applicable for binary image skeletonization, Voronoi tessellation or distance transformation tasks where calculating distances in a particular metric (e. g. Euclidean, Manhattan, Chessboard, etc.) is desired.

Oguzhan Yavuz, Nergis Tural Polat, Evren Cesur and Vedat Tavsanoglu

3-D Spatio-temporal Gabor-Type Filter Implementations with Time-Derivative Cellular Neural Networks

In this paper, a 3-D spatio-temporal Gabor-type filter is implemented using Time-Derivative Cellular Neural Network (TDCNN) structure. To this end, the transfer function of the spatio-temporal filter previously constructed by cascading a CNN spatial filter with a temporal filter is shown to be made equal to that of a band-pass filter obtained using a TDCNN structure having first-order temporal derivative diffusion connections only. By equating the coefficients, we obtain the discrete-space Fourier transforms of the TDCNN templates of the Gabor-type band-pass filter. Taking the inverse Fourier transform yields the TDCNN templates. Simulation results are presented.

Natsuno Kazushige, Yoko Uwate and Yoshifumi Nishio

Motion Picture Processing by Two-Layer Cellular Neural Networks with Switching Templates

In this paper, we investigate characteristics of output values by a proposed new system of two layer cellular neural networks (two-layer CNN). In a general way, image processing of using conventional cellular neural networks is still image processing. On the other hand, it is few for motion picture processing. Therefore, we propose the new system which is effective structure for motion picture processing. From simulation results, we confirm that the proposed system makes it possible to characterize the time course characteristic of moving object.

Chaos and Bifurcation

Yoko Uwate, Yoshifumi Nishio and Thomas Ott

Clustering Phenomena in Coupled Chaotic Circuits with Different Coupling Strength

In this study, we investigate synchronization phenomena in coupled chaotic circuits with different coupling strength when chaotic circuits are arranged irregularly in one dimensional array. Three groups are composed in this circuit system and each group includes some chaotic circuits. The coupling strength corresponds to the distance between the chaotic circuits. We observe several types of synchronization states when the coupling strength is fixed to appropriate value.

Daichi Manabe and Tadashi Tsubone

Analysis of a Controlled 3-D Piecewise-Constant Circuit with time-delayed feedback

In this study, we consider a hysteresis piecewise-constant circuit with feedback of time-delayed states. In general, it is relatively hard to treat a continues-time dynamical system with time-delayed components in theoretical sense. Since the behavior of our proposed system is governed by piecewise-constant vector field, the stability of the system can be analyzed based on the geometric approaches of the phase space. In this paper, we consider a stabilizing control of unstable periodic orbits by time-delayed feedback and analyze the stability. We derive a piecewise linear map to describe the system dynamics in a neighborhood of a periodic orbit and show analytical results on the stability.

Shota Kirikawa and Toshimichi Saito

Filter-induced Bifurcation in Simple Spiking Circuits

This paper studies filter-induced bifurcation phenomena in simple spiking circuits. Repeating integrate-and-fire dynamics between a periodic base signal and a threshold, the circuit outputs spike-trains. The dynamics depends crucially on the shape of the base signal and we make the base signal by filtering a square source signal. As a key parameter of the filter varies, the shape of the base signal varies and the model can exhibit bifurcation phenomena of various periodic/chaotic spike-trains. Effects of the ideal low-pass filter is considered. Presenting a simple test circuit, typical phenomena are also confirmed experimentally.

Ihsan Cicek and Gunhan Dundar

A Chaos Based Integrated Jitter Booster Circuit for True Random Number Generators

In this work, we present a chaos based integrated jitter booster circuit for use in multiple oscillator sampling true random number generator architecture. Multiplering oscillator based true random number generators need significant number of rings for accumulating the intrinsic jitter of inverters to a useful level. Thus, they occupy large silicon area and consume considerable amount of power. The proposed circuit offers an alternative approach for boosting jitter using the chaotic dynamics generated by non-linear coupling of two ring oscillators that require fewer number of components. The simplicity of the proposed circuit offers high integration potential with inherent low area and power consumption advantages. Chaotic dynamics of the circuit was studied using both numerical and circuit simulations. Measurement results of the test chip implemented at 250nm CMOS technology node confirmed chaotic behavior and jitter boosting capability. To the very best of our knowledge this is the first integrated circuit implementation of a chaotic circuit based on digital gates.

Ramazan Yeniceri, Buse Ustaoglu and Mustak Erhan Yalcin

Throughput Enhancement for a New Time-delay Sampled-data System Based True Random Bit Generator

In this paper, a throughput enhanced version of a new True Random Bit Generator (TRBG) based on a time-delay sampled-data system is proposed. This new TRBG has both analog and digital parts, which provides the dynamic behavior and the sample and delay process, respectively. The simple system equations and the ease of implementation make this new TRBG very practical. The only required components for the implementation of the proposed system is commonly used Op Amps, resistors and capacitors with a chain of D type flip-flops. The main contribution of this paper is the increase in random bit generation rate provided by operating two identical but unsynchronized circuits compared to the single circuit setup. As experienced, a 2.5 times greater random bit generation rate is achieved by this approach. In order to measure the statistical performance, the contemporary NIST 800-22rev1a Statistical Test Suite is used and it is experienced that the throughput enhancement is achieved with pass results from all these statistical tests.

Filter Design 1

Miroslav Vlcek and Pavel Zahradnik

Approximation of Almost Equiripple Low-pass FIR Filters

A novel approximation of a linear phase almost equiripple low-pass finite impulse response filter is introduced. Its frequency response closely approaches the frequency response of an optimal equiripple low-pass finite impulse response filter. The presented approximation is based on the generating polynomial, which is related to the class of iso-extremal polynomials. The closed form solution for an algebraic evaluation of the impulse response of the filter has been developed on the basis of a generalization of the differential equation suitable for halfband specifications. No numerical procedures are involved. The practical design procedure based on the developed approximation is presented. An example of the design is included.

Shotaro Nishimura, Aloys Mvuma and Takao Hinamoto

Complex Adaptive Notch Filters for Frequency Estimation of Three-Phase Power Systems

This paper presents a new technique for adaptive estimation of the frequency of unbalanced three-phase power systems using complex coefficient first-order notch filters. The input complex sinusoid is given by a sum of sequences with positive and negative frequencies. The analytical expression of a estimation error oscillation introduced by the sequence with negative frequency has been derived. Closed form expression for frequency tracking error has been also derived for a complex linear chirp signal. Computer simulation results are presented to validate the analysis.

Radu Matei

Design of 2D Parametric Filters for Directional Gaussian Smoothing

This paper proposes an analytical design method for a class of 2D recursive filters, namely filters for Gaussian smoothing. These filters have a Gaussian shape in a vertical section and an elliptical shape in a horizontal section, parallel with the frequency plane, with a specified orientation angle. The design is based on decomposing the frequency response into three simple Gaussian components along the frequency axes and diagonal. For each of the components the transfer function is found applying an efficient pre-warping before using the bilinear transform, which allows obtaining filters without any distortions. Finally the filter matrices are obtained. The filter is adjustable in the sense that its characteristics are specified by parameters which appear explicitly in the filter coefficients.

Takao Hinamoto, Akimitsu Doi and Wu-Sheng Lu

Jointly Optimal High-Order Error Feedback and Realization for Roundoff Noise Minimization in 2-D State-Space Digital Filters

The joint optimization problem of high-order error feedback and realization for minimizing roundoff noise at filter output subject to l_2-scaling constraints is investigated for two-dimensional (2-D) state-space digital filters. Linear algebraic techniques that convert the problem at hand into an unconstrained optimization problem are explored, and an efficient quasi-Newton algorithm is then applied to solve the unconstrained optimization problem iteratively. In this connection, closed-form formulas are derived for fast and accurate gradient evaluation. Finally a numerical example is presented to illustrate the validity and effectiveness of the proposed algorithm.

Chien-Cheng Tseng and Su-Ling Lee

Fractional Derivative Constrained Design of FIR Filter with Prescribed Magnitude and Phase Responses

In this paper, the designs of fractional derivative constrained FIR filters with prescribed magnitude and phase responses are presented. First, the definition of fractional derivative is reviewed. Then, FIR filters with complex-valued frequency responses are designed by minimizing the integral squares error under the constraint that the actual response and ideal response have several same fractional derivatives at the prescribed frequency point. Finally, the designs of low group delay low-pass filter and Hilbert transformer are demonstrated to show the effectiveness of the proposed design method.

Filter Design 2

Chien-Cheng Tseng and Su-Ling Lee

Design of Sparse Lowpass Differentiator Using Iterative Hard Thresholding Method

In this paper, the design of a sparse digital lowpass differentiator is presented. First, the original iterative hard thresholding (IHT) algorithm in the compressed sensing is used to solve this design problem. Then, a modified IHT algorithm is proposed to improve the performance by using a smooth thresholding technique. Finally, the proposed IHT methods are compared with the conventional orthogonal matching pursuit (OMP) method to show their performance. The main feature of the proposed design methods is that the error of magnitude response and sparsity of filter coefficients can be controlled by suitably choosing the thresholding parameter.

Pietro Monsurrò, Salvatore Pennisi, Giuseppe Scotti and Alessandro Trifiletti

Effect of components relative tolerance in the magnitude response of a Gm-C biquad

We analyze the effects of relative mismatches in transconductances and in capacitances onto the magnitude of the Gm-C biquad filter section. It is confirmed that deviation from the ideal magnitude increases with Q and with mismatches, being those associated with transcondunctances the relevant ones. The obtained data can be used at an early design stage to limit the magnitude error of a cascaded filter to a specified value by limiting the Q factor of each biquad.

Timo Rahkonen, Janne Aikio and Jose Carlos Pedro

Comparison of Time-Domain and Frequency Domain Polynomial Fitting

Polynomial models for transistor I-V curves are needed for example for Volterra analysis. The polynomial models can be fitted with least-square error techniques using DC data, measured time-series, or measured spectra. This paper shows that with sufficiently broadband spectrum measurement the time-domain and frequency-domain fitting techniques result in the same model. It was also demonstrated that lot of spectral content can be discarded during the fitting, and still achieve the same fit.

Carlos Sanchez-Azqueta and Santiago Celma

Design Criteria for Loop Filters in Spectrum Balancing Technique-Based Adaptive Equalisers

Equalisation is mandatory in modern high-speed communications systems; among the different techniques proposed in the literature, adaptive equalisation at the receiver based on the power spectrum balancing technique is the preferred solution because of its capability to take into account the varying channel characteristics and its low power requirements. This paper presents an overview of the different structure that are used in the literature, establishing measureable design criteria for the filters based on the characteristics of the channel and the equalizer filter.

Peter Nilsson, Anusha Gundarapu and S. M. Yasser Sherazi

Power Savings in Digital Filters for Wireless Communication

This paper presents a methodology to reduce the power consumption, silicon area, as well as increasing the performance, in digital filters that are feasible for wireless communication circuitries. The method is based on arithmetic reductions in a wave digital filter. Basically, the multipliers are removed to reduce the number of arithmetic operations. All parameters including the dynamic and static power consumption, the silicon area, as well as the delay time are reduced substantially, without any need for trade-offs. The overall improvements in area, power consumption, and delay time, are around 50%, at an average.

Demo & Poster

Johannes Partzsch, Alexander Rast, Christian Mayr, Luis Plana, Bernhard Vogginger, Rene Schüffny and Steve Furber

Live Demonstration: Ethernet Communication Linking Two Large-Scale Neuromorphic Systems

With neuromorphic hardware rapidly moving towards large-scale, possibly immovable systems capable of implementing brain-scale neural models in hardware, there is an emerging need to be able to integrate multi-system combinations of sensors and cortical processors over distributed, multisite configurations. We propose a UDP-based AER spiking interface that permits direct bidirectional spike communications over standard networks, and demonstrate a practical implementation with two large-scale neuromorphic systems, BrainScaleS and SpiNNaker. The system is able to run a spiking neural network distributed over the two systems, in both a side-by-side setup with a direct cable link and over the Internet between 2 widely spaced sites. Such a model not only realises a solution for connecting remote sensors or processors to a large, central neuromorphic simulation platform, but also opens possibilities for interesting automated remote neural control, such as parameter tuning, for large, complex neural systems, and suggests methods to overcome differences in timescale and simulation model between different platforms. With its entirely standard protocol and physical layer, the interface makes large neuromorphic systems a distributed, accessible resource available to all.

Live Demonstration: Method of Modeling Analog Circuits in Verilog for Mixed-signal Design Simulations

Sebastian Höppner, Dennis Walter, Holger Eisenreich, Stefan Schiefer and René Schüffny

Live Demonstration: A 90GBit/s Serial NoC Link over 6mm in 65nm CMOS Technology

A source synchronous network-on-chip link with 90GBit/s total data rate (10GBit/s/lane) over 6mm in 65nm LP CMOS technology is presented. It achieves an energy efficiency of 173fJ/bit/mm at 90GBit/s from 1.25V supply and 93fJ/bit at 45GBit/s from 0.9V supply. Within this live demonstration link parameters such as supply voltage, link speed and signal voltage swing on the physical line can be varied interactively to demonstrate the scaling capability of this link architecture.

Shuitsu Matsumura

Efficient Multistage Implementation of Rational Sampling Rate Converter

In Digital audio processing, there are multiple standard sampling rates, for example, 48kHz for studio work, 44.1kHz for compact disk(CD) mastering. Therefore, sampling rate conversion is needed to interchange signals from one field to another. A rational sampling rate conversion by L/M can be done cascading an L-fold up-sampler and an M-fold down-sampler with a linear phase FIR lowpass filter in the middle. When both L and M have large values, the lowpass filters are required to have an extremely narrow normalized bandwidth and a sharp transition characteristic, causing difficulty in design and implementation. This paper describes a technique to overcome this difficulty for the case both L and M are composite numbers, giving an multistage converter structure where each stage is consisting of an up-sampler and a down-sampler, both of a small conversion ratios, with a filter having not so sharp normalized transition characteristic in the middle, remarkably reduced total computation complexity.

Federico Bizzarri, Angelo Brambilla, Stefano Saggini and Giancarlo Storti Gajani

Mixed-Mode Simulations to Check Stability of an Adaptive Constant On-Time DC-DC Converter

In this paper we consider performances of a version of a constant on-time (COT) DC/DC converter. There is a renewed interest in COT converters since they offer interesting features such as speed and low cost implementation. The duty cycle of these converters is varied by acting on the working frequency and this introduces problems in modeling, in deriving transfer functions and in studying stability properties. Largely adopted averaging methods, that assume that the control loop bandwidth is much smaller than the converter switching frequency, risk to be no longer applicable since COT converters do not satisfy this hypothesis. Also conventional methods and techniques that exploit Floquet theory and variational models can not be applied since differential algebraic equations modeling switching converters show discontinuities in the vector field (switching). In this paper we use saltation matrices to allow the application of consolidated numerical techniques to the specific case of COT converters and, more in general, to the broad class of switching converters modeled by mixed analog/digital models.

Cecilia Gimeno, Carlos Sánchez-Azqueta, Santiago Celma, Concepción Aldea and Ciaran Cahill

A 1.25 Gb/s Fully Integrated Optical Receiver for SI-POF Applications

This paper presents the design of a 1.25 Gb/s fully integrated BiCMOS optical receiver for short reach applications through low-cost step index plastic optical fiber. The limited bandwidth caused by the fiber is compensated by a continuous-time equalizer. A low noise transimpedance amplifier with some peaking overcomes the limitation introduced by the integrated photodiode. A post-amplifier has been included to generate the required digital output levels. The design achieves 1.25 Gb/s through 50 m POF with a power consumption of 148 mW and a sensitivity of -16.4 dBm for a BER of 10-12.

Tomoharu Nagashima, Kazuhide Inoue, Xiuqin Wei, Elisenda Bou, Eduard Alarcon and Hiroo Sekiya

Inductively Coupled Wireless Power Transfer With Class-E^2 DC-DC Converter

This paper proposes an inductive coupled wireless power transfer (WPT) system with class-E^2 dc-dc converter along with its design procedure. The proposed WPT system can achieve high power-conversion efficiency at high frequencies because it satisfies the class-E zero-voltage switching and zero-derivative-voltage switching conditions on both the inverter and the rectifier. By using the class-E inverter as a transmitter and the class-E rectifier as a receiver, high power-delivery efficiency can be achieved in the designed WPT system. By using a numerical design procedure proposed in the previous work, it is possible to design the WPT system without considering the impedance matching for satisfying the class-E ZVS/ZDS conditions. The experimental results of the design example showed the overall efficiency of 85.1 % at 100 W output power and 200 kHz operating frequency.

Alberto Oliveri, Matteo Lodi and Marco Storace

Design and circuit implementation of approximate switched MPC

This paper proposes a novel method for design and circuit implementation of approximate controllers for constrained hybrid or piecewise affine (PWA) systems, through switched model predictive control technique. The PWA solution (discontinuous, in general) provided by this method is approximated by another PWA function composed of continuous patches defined over regular simplices. Two circuit architectures for the implementation of this approximate controller are proposed,which allow achieving reduced complexity and shorter latency, with respect to the circuits implementing the exact controller. This makes it possible the control of systems with smaller sampling times. The performances of the approximate controller are shown through hardware-in-the-loop testings of the closed-loop system.

Poster

Stefan Haenzsche and René Schüffny

Analysis of a Charge Redistribution SAR ADC with Partially Thermometer Coded DAC

This paper presents an analysis of capacitor mismatch of a partial thermometer coded charge redistribution SAR ADC. Thermometer coding of only the most significant bits effectively improves the linearity of a binary weighted capacitor array without a exponential growth of decoder and interconnection effort at high resolutions. Distribution based calculations and an implementation example demonstrate the increase of chip yield or the possible reduction of circuit area. The proposed approach can be applied to different conventional architectures and requires only small additional decoder logic.

Lufei Shen and Klaus Hofmann

Design Strategies for Integrated High Voltage Charge Pumps

Design strategies in analyzing important design factors of integrated high voltage charge pump circuits are presented in this paper. By using concrete examples, this paper is supposed to provide a solid understanding of the design constraints during the integrated high voltage charge pump design tasks and to be beneficial for circuit optimization.

Emilie Avignon-Meseldzija, Sylvain Azarian, Stéphane

Font and Marc Lesturgie

Modeling and Optimization of a Dedicated FMCW Radar Frequency Synthesizer

This paper presents the modeling and optimization of a frequency synthesizer dedicated to FMCW radar applications. This frequency synthesizer based on a type-I PLL presents the advantages of a simplified architecture with less potential electronic drawbacks. A methodology to optimize the filter loop is proposed in order to obtain the required smoothed frequency characteristic and correct the VCO distortion.

Victor R. Gonzalez-Diaz, J. F. Guerrero-Castellanos, Gerardo Mino-Aguilar and Aldo Pena-Perez

Compact Implementation of a Three Stages Feedforward Operational Transconductance Amplifier with Miller Compensation

This work proposes a novel implementation for a three stages Operational Transconductance Amplifier with feedforward g_m paths. The proposed solution enhances the amplifier’s Gain-Bandwidth product and enables capacitive Miller compensation with no appearance of a Right-Half-Plane zero on its transfer function. The main difference with state of the art topologies is that instead of canceling zeroes it locates a Left-Half-Plane zero without using zero nulling resistor or additional active stages, therefore improving phase, speed, output swing and reliability on compensation with a minimum increase of power consumption.

Hourieh Attarzadeh and Trond Ytterdal

Low Power OTA-Less I-V-converter with Single-Ended To Differential Conversion for Capacitive Sensor Interfaces

this paper presents a current-mode interface circuit for capacitive sensors, with the main feature of being able to produce a differential output voltage from a single-ended capacitive sensor. The circuit has been designed combining two concepts of Folded Current Mirror and Charge Sampling. A total harmonic distortion of 34db over a 5-MHz signal bandwidth, and a DR of 48db are estimated. The circuit consumes only 60uA from a 1.5V supply. The efficiency of the proposed scheme is evaluated in a 130nm CMOS technology from Global Foundries.

Piotr Zegarmistrz and Zbigniew Galias

Reconstruction of conductances in resistive grids as an optimization problem

In this work, the problem of reconstruction of conductances in resistive grids is studied. It is assumed that access is available to boundary nodes only. The problem is stated as an optimization problem. An objective function is defined and its properties are discussed. The performance of several optimization methods for solving the reconstruction problem is evaluated for square and non-square resistive grid. The algorithms are compared in terms of numerical stability, accuracy of the results and the computation time. Possible applications of the proposed algorithms are discussed.

Melike Atay and Mustak Erhan Yalcin

A Parallelized Distance Transformation Architecture for FPGAs

Object detection, object recognition, shape matching and path planning are important tasks in computer vision systems. Distance transformation is an algorithm commonly utilized in such systems. In this paper, a new FPGA based distance transform implementation is proposed to be used in object recognition and shape matching systems. The proposed method is designed to meet high performance, low power and low area requirements. The Xilinx Spartan-6 FPGA is preferred for the implementation.

Jordi Cosp-Vilella and Herminio Martínez-García

On Chaotic Behavior in Automatic Tuning Loops for Continuous–Time Filters

Continuous–time filters (CTFs) with automatic tuning loops are nonlinear feedback systems with potential instability. Thus, their appropriate linear dynamic modeling should be obtained to assure stability in case of an improved design of the loop controllers is to be carried out. A systematic approach using a small signal model would allow obtaining these controllers, however, bifurcations and nonlinear phenomena may appear, which cannot be predicted by this analysis. This leads to potential instability, semiperiodic or chaotic behavior and, thus, circuit malfunction.The aim of this paper is to show by means of simulations and experimental results that nonlinear phenomena, which cannot be predicted by the common small signal analysis, may appear in this kind of circuits when parameters are varied.

Yang Jiao, Weimin Li, Dianwei Zhang and Wu Wen

A 70 dBohm 2.3 GHz low noise Transimpedance Amplifier

A low-noise transimpedance amplifier (TIA) for 2.5 Gb/s family is presented using 0.35 um BiCMOS technology. It would be used in radiation detectors to transform the current pulse produced by a photo-sensitive device into an output voltage pulse with a specified amplitude and shape. In this paper the mathematical analysis of the proposed TIA is presented together with a detailed analytical noise optimization. For the gain boosting, Cherry-Hooper amplifier is introduced for the second stage amplification. Aslo a method for eliminating the DC current of the input photodiodes (PDs) is proposed. The chip measured results show the TIA achieves a constant gain of 70 dBohm from 65 kHz to 2.3GHz when connected to a 0.85 pF load, average input referred noise of 2.6 pA/sqrt(Hz) up to 0.8 GHz, 18 mA supply current at +3.3 V including the output buffer. The die size is 30milx50mil.

Bartlomiej Garda and Zbigniew Galias

Coil shape design using the quasi-Newton algorithm

The problem to find the shape of the coil to obtain the required magnetic field in a given area is studied. It is assumed that the coil has cylindrical symmetry, and that the current density in the coil is fixed. Two cases of the shape of the target area are considered. When the target area is located on the coil axis, the problem can be simplified by using analytical formula for the the magnetic field. In a general case when the target area is located outside of the coil axis numerical integration is used to compute magnetic field in the target area. The quasi-Newton method is used to solve the resulting nonlinear optimization problem. It is shown that this optimization method works properly in both cases. Several design examples are presented.