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FAQ

Q1. For which kind of design community HICUM is useful?
A1. For those who intend to design circuits at high frequency and high current regions. HICUM relies on physics-based model equations and is geometry-scalable.

Q2. What do the different levels and different versions of HICUM signify?
A2. Levels signify major differences in the model formulation, consisting of the equivalent circuit and the equations for its elements. The version differences in a same level are due to major modifications in the model formulation. The last number (e.g. "0", "1" etc) signifies minor code modifications (bug-fix, optimization etc) of the same version.

Q3. Can I get the DEVICE or HICUMNA code?
A3. The mixed-mode simulator DEVICE along with its FTN model code, for version 2.2 and later, can only be provided to the cooperation partners of our research group due to the lack of support manpower for a large group of users.

Q4. What code is taken as a reference for the model implementation/testing?
A4. Verilog-A code given in the Source Code section of this webpage, is considered as the reference for model implementation and testing. Some reference test data are also given inside the Model Testing & Results section.

Q5. Can I get the SPICE3F code of HICUM?
A5. HICUM implementation in SPICE3F (C code) was performed by Prof. J.-C. Perraud at the university of Caen, France. If you are interested in SPICE3 as a reference, you may contact him at perraud@ecole.ensicaen.fr..

Q6. Why Verilog-A is chosen for model release?
A6. This enables with the most efficient path for quick model release, test and implementation. Using a model compiler, a uniform implementation across all the commercial simulators can be ensured. Furthermore, test data can be generated by the implementation person itself. Commercial simulator implementation should match the verilog results. Suitable test parameters, netlists, test results and selected test data are also provided on the web within the release package. Note, that due to the fact that every simulator has a different interface and model data structure there cannot be an optimized C code provided by the model developer for each existing simulator. For more clarification on this topic, one is encouraged to look into the release_format.pdf.

Q7. How one can get the derivative (useful for the small-signal model) from the Verilog-A code?
A7. Using the automated C-code generator, one can get all the required derivatives. One can use ADMS and related Xml scripts to get a complete compiled model.

Q8. What is the nomenclature style for the netlists and the ASCII data files avalable on the website?
A8. The ASCII data given in the website follows the convention:
General format: Netlist_name_x_y.elpa where,
y=1: T=300K
y=2: T=200K
y=3: T=400K
y=4: T=600K
y=5: Electrothermal/Self-heating effect
y=6: NQS effect
y=7: Collector current spreading effect
y=8: Substrate transistor effect without substrate network
y=9: Effects with substrate transistors and substrate network
and
x=1: Intrinsic transistor
x=2: Internal Transistor:
Thermal data for x=2:
y=3: T=200K, y=4: T=400K, y=5: T=600K, y=6: T=300K.
x=3: Complete transistor

Q9. In the netlists, value of some parameters p4, p5, p6 are missing. What will be the values?
A9. In DC simulation, the format is: [p1 p2 p3 p4 p5]

Netlists and the corresponding sweep information are given here:

netlist='rg_vec'
sweep(1,:)=[0.2 1.0 40 2.0 0]

netlist='ro_vec'
sweep(1,:)=[0.0 5.0 25 0.6 0]
sweep(2,:)=[0.0 5.0 25 0.7 0]
sweep(3,:)=[0.0 5.0 25 0.9 0]
sweep(4,:)=[0.0 5.0 25 1.0 0]

netlist='fg_vce'
sweep(1,:)=[0.0 1.2 60 0.5 0]
sweep(2,:)=[0.0 1.2 60 2.5 0]

netlist='fo_ib'
sweep(1,:)=[0.0 8.0 40 10.0E-6 0]
sweep(2,:)=[0.0 8.0 40 100.0E-6 0]
sweep(3,:)=[0.0 8.0 40 1.0E-3 0]
sweep(4,:)=[0.0 8.0 40 5.0E-3 0]
sweep(5,:)=[0.0 8.0 40 10.0E-3 0]
sweep(6,:)=[0.0 8.0 40 50.0E-3 0]

netlist='fo_vce'
sweep(1,:)=[0.0 8.0 40 0.6 0]
sweep(2,:)=[0.0 8.0 40 0.7 0]
sweep(3,:)=[0.0 8.0 40 0.8 0]
sweep(4,:)=[0.0 8.0 40 0.9 0]
sweep(5,:)=[0.0 8.0 40 1.0 0]
sweep(6,:)=[0.0 8.0 40 1.1 0]
sweep(7,:)=[0.0 8.0 40 1.2 0]

In AC simulation, the format is: [p1 p2 p3 p4 p5 p6]

netlist='ac_mf_log_vbc'
sweep(1,:)=[1.0e5 25e9 10 0.8 0.3 0.0]
sweep(2,:)=[1.0e5 25e9 10 0.86 0.3 0.0]
sweep(3,:)=[1.0e5 25e9 10 0.91 0.3 0.0]
sweep(4,:)=[1.0e5 25e9 10 0.86 0.5 0.0]
sweep(5,:)=[1.0e5 25e9 10 0.86 -1.0 0.0]
sweep(6,:)=[1.0e5 25e9 10 0.86 -5.0 0.0]

netlist='ac_mb_vbc'
sweep(1,:)=[0.6 1.0 20 0.5 2.8E9 0.0]
sweep(2,:)=[0.6 1.0 20 -1.5 2.8E9 0.0]
sweep(3,:)=[0.6 1.0 20 -2.5 2.8E9 0.0]
sweep(4,:)=[0.6 1.0 20 -5.0 2.8E9 0.0]

Q10. Why are not all the test data provided in ASCII format? How can I get all those?
A10. Most of the test data are provided. But in principle, one can independently generate any test data using the available Verilog-A code at his/her end.

Q11. What are the default and test parameters?
A11. Default parameters are the ones available inside the model (e.g. the Verilog-A model). The default parameters are set in such a manner that the model behaves effectively as a simple transport model.
Test parameters are those parameters that are used to investigate the various combinations of modeling effects possibly seen in the actual transistor. Test parameter sets are given in the Source Code section.

Q12. How are the ranges of the model parameters selected?
A12. The ranges of the model parameters provide sensible boundaries of the parameter values to ensure realistic and numerically acceptable values.

Q13. Why is the stand-alone kit not provided as the main released model and supported accordingly?
A13. Verilog-A release form is superior to FTN code. A smart compiler can convert the model code into C-code uniformly over all the commercial simulators. See A4 above.

Q14. Is the NQS effect implemented in HICUM?
A14. HICUM version 2.1 in all simulators contains the NQS model implementation. Up to now no NQS effect has been implemented in the released Verilog-A code. This will be included and released once a suitable way for correct implementation of NQS effects (charge and transfer current) is available.

Q15. How is the heat generation for the self-heating effect implemented in HICUM?
A15. At present only the effects of transfer and avalanche current sources are taken into account in modeling the self-heating in HICUM. Our experience has shown that the effects of the other current sources are negligible. Effects of other sources are included in the model on a conditional basis (flag FLSH=2).

Q16. What is TRADICA and how one can get that?
A16. TRADICA is a scalable model library development tool. For more information, one may look into the TRADICA page. To get access to this tool, one is also requested to visit XMOD Technologies.

Q17. How is the operating point information for the transistor defined?
A17. The operating point information is given inside the Documentation section.

Q18. What is Level4 HICUM model meant for?
A18. Level 4 model is meant to take care of the distributed electrical and thermal effects inside the actual device. At the cost of the CPU time, this model provides accuracy in some specific types of circuits.

Q19. What is a model compiler and what for is it made? Where from can I get information on compilers?
A19. A model compiler enhances various operations, of which most interesting part is its capability to automatically generate a uniform C-code from the Verilog-A model code. This solves many problems. From Compiler section, one can get some useful links for model compilers.

Q20. What are the differences in the charge terms Q_p and Q_pT and what are their significances in HICUM?
A20. There is sometimes confusion about the use of the hole charge terms Q_p and Q_pT in various equations and modes of operation. The term Q_p represents the stored charge in the transistor. This charge is used in transient analysis, and its derivatives define the capacitances to be used in small-signal analysis.
The term Q_pT consists of a weighted sum of the charge contributions from various transistor regions. According to the GICCR, which is derived directly from the transport equation, this term is used in the denominator of the transfer current formulation.

Q21. What is limexp() function and how does it differ from standard exp() function?
A21. According to the Verilog-AMS manual, the apparent behavior of limexp() is not distinguishable from exp(), except using limexp() to model semiconductorjunctions generally results in significantly improved convergence.
The limexp() function is an operator whose internal state contains information about the argument on previous iterations. It returns a real value which is the exponential of its single real argument, however, it internally limits the change of its output from iteration to iteration in order to improve convergence. On any iteration where the change in the output of the limexp() function is bounded, the simulator is prevented from terminating the iteration. Thus, the simulator can only converge when the output of limexp() equals the exponential of the input.

Q22. Is Correlated noise implemented in HICUM?
A22. The implementation of correlated noise in HICUM is currently under development and hopefully will be released in near future.



A.Mukherjee, L.Hofmann
14 September 2010